Chip Industry Week in Review


Cadence plans to buy Hexagon AB's design and engineering business to accelerate expansion in physical AI and system design and analysis. Cadence will pay ~US$3.1 billion in cash and issue stock, with the deal expected to close in early 2026. PWC issued a 104-page in-depth analysis of semiconductor technology and markets, highlighting a broad swath of changes: $1T in annual revenue by 2030, ... » read more

Agile Development Of Software-Defined Vehicles Using Cloud-Based Virtual Prototypes


By Gunnar Braun and Stewart Williams Automotive software is becoming more expensive and central to a car’s identity. Infotainment, advanced driver-assistance systems (ADAS), traction control, and even powertrain management are all shaped by lines of code. Vehicular codebases can now exceed those of commercial aircraft! The growing adoption of electric vehicles (EVs) and the push toward ful... » read more

6G Line-Of-Sight Repeaters, Dots, And Reflections


6G will open the door to ultra-reliable, low-latency communications, extended broadband, and machine communications, but its rapid signal attenuation places some sharp limits on where and how it can be used, and requires some expensive options to overcome those limitations. Applications include lifelike virtual reality for home and work use, highly interactive smart homes and cities, and aut... » read more

Cloud vs. Edge Gaming: Performance Gap Is Shrinking


Chip designers and gaming companies are scrambling to figure out whether the gaming market will tilt toward the cloud, the edge, or some combination of both. Multi-gigabit internet allows more people to play high-end games in the cloud, but edge-based gaming consoles and devices remain well-rooted, more secure, and private. Which one wins? So far, there are more questions than answers. Handh... » read more

Security Requirements And Penalties Grow For Chipmakers


Governments and systems companies are fundamentally changing the rules around semiconductor security, forcing chipmakers and their suppliers to comply with tough new regulations that require resiliency in hardware. Unlike in the past, chips and systems deployed in these markets must be able to respond to threats rather than waiting for the next version of a chip or IP to address vulnerabilities... » read more

The Criticality of Performance per Watt Optimization for AI Chip Development


Chip developers are seeing an urgent rise in demand for compute processing capability driven by AI workloads. This increase in compute requirements drives a corresponding increase in the demand for power consumption. For example, a ChatGPT query requires nearly 10 times as much power, on average, as a Google search. Power has traditionally been treated as a secondary constraint, with perform... » read more

Blog Review: September 3


Cadence's Sriram Sharma Kalluri compares convolutional neural networks (CNNs) and transformers to show how their different architectures give them particular strengths and why the choice between them depends on the specific task, the available data, and the computational resources. Siemens' John McMillan provides a primer on the major IC package types, how they influence system design, therm... » read more

AI’s Value In Chip Design Depends On Data Availability


Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of product marketing and senior director for custom IC at Siemens EDA; Anand Thiruvengadam, senior director and head of AI product management at Synopsys; Sailesh Kumar, CEO of Baya Systems; Mehir ... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Chiplet Design Considerations


Chiplets are a way to offer continuing increases in compute capacity and I/O bandwidth needs by splitting SoC functionality into smaller heterogeneous or homogeneous dies called chiplets and integrating these chiplets into a single system in package (SIP), where the total silicon content can exceed the reticle size of a single SoC. SIP includes traditional package substrates but also may includ... » read more

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