tag: Synopsys

Government Funding For Chip Design Tools Spreads
By Liz Allan - 28 Aug, 2025 - Comments: 0

Governments around the globe are starting to invest more heavily in chip design tools and related research as part of an effort to boost on-shore chip production, opening new opportunities for startups and established EDA companies. Those cash infusions, which are being doled out in the U.S., Europe, and Asia, are part of a growing recognition of the importance of design automation tools wit... » read more

Silicon Lifecycle Management Gains Traction, But It’s Complicated
By Ann Mutschler - 28 Aug, 2025 - Comments: 0

Silicon lifecycle management (SLM) is gaining ground in semiconductor design and test by leveraging specialized on-die sensors and analytics engines to improve power, performance, yield, and reliability. Most modern SoCs mitigate the guesswork by leveraging DFT, which includes adding memory built-in self-test (BiST) or improving functional coverage, but these tests were meant for verifying c... » read more

Verification Fails To Keep Up
By Brian Bailey - 28 Aug, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss the state of functional verification with Mohan Dhene, director for architecture and design at Alphawave Semi; Andy Nightingale, vice president for product management and marketing at Arteris; Dinesha Rao, senior group director for software engineering at Cadence; Chris Mueth, new opportunities business manager at Keysight; Gor... » read more

Physical Access Control Raises New Security Concerns
By Ann Mutschler - 27 Aug, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering sat down to discuss hardware security challenges, including fundamental security of GenAI, with Nicole Fern, principal security analyst at Keysight; Serge Leef, AI-For-Silicon strategist at Microsoft; Scott Best, senior director for silicon security products at Rambus; Lee Harrison, director of Tessent Automotive IC Solutions at Siemens EDA; Mohit... » read more

Blog Review: August 27
By Jesse Allen - 27 Aug, 2025 - Comments: 0

Cadence's Pamula Sai Srinivas explains why clock tree synthesis is essential to ensuring that the clock signal is distributed in a way that helps achieve timing closure and maintain synchronization, performance, and reliability. Synopsys' Sajani Patel, Varun Agrawal, and Manuel Mota check out what's new in UCIe 3.0, including doubling the maximum data rate to 64 GT/s, runtime recalibration, ... » read more

Benchmark Before You Build
By Synopsys - 27 Aug, 2025 - Comments: 0

Traditional verification methods, static analysis, RTL simulation and emulation have long depended on constrained-random or targeted test suites to confirm that a design operates as intended. However, none of these approaches accurately reproduce how real users will interact with the silicon once it’s deployed in phones, datacenters, or embedded systems. To stay competitive, the semiconductor... » read more

Materials Modeling Of Superconducting Qubits In Quantum Computers
By Anders Blom - 21 Aug, 2025 - Comments: 0

While the concept of quantum computing has been discussed for more than 40 years, only recently have experiments indicated that a practical quantum computer may be possible. Recent developments in this area have captured headlines with dramatic claims—and equally dramatic rebuttals. Google’s Willow chip demonstrated error-corrected operations in late 2024, while D-Wave’s assertion of quan... » read more

Manufacturing At The Limits
By Gregory Haley - 21 Aug, 2025 - Comments: 2

Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

Reticle Stitching Bumps Up Silicon Interposer Costs
By Bryon Moyer - 21 Aug, 2025 - Comments: 0

Advanced packaging often relies on silicon interposers to connect chiplets and other components inside a package. The problem is that interposers typically exceed the reticle limit, which adds both complexity and cost. An interposer is essential for 2.5D and 3.5D architectures. As device scaling runs out of steam, chipmakers are decomposing planar SoCs into chiplets and connecting them throu... » read more

Blog Review: August 20
By Jesse Allen - 20 Aug, 2025 - Comments: 0

Cadence's Sriram Sharma Kalluri finds that time-of-flight sensors are poised to revolutionize ADAS by generating precise 3D point clouds that, particularly when combined with lidar, contribute to an exceptionally accurate and comprehensive understanding of the vehicle's surroundings. Synopsys' Igor Markov and other industry experts discuss how quantum computing is moving from research to p... » read more

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