tag: Synopsys

Where Do We Stand With CDC
By Ann Mutschler - 29 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of [getentity id="22674" e_name="Arteris"]; Shaker Sarwary, VP of Formal Verification Products at [getentity id="22026" e_name="Atrenta"]; Pranav Ashar, CTO at [getentity id="22416" e_name="Real Intent"]; and Namit Gupta, CAE, Verification Group at [getentity id="22035" e_nam... » read more

The Week In Review: Design
By Ed Sperling - 26 Sep, 2014 - Comments: 0

Tools Synopsys rolled out a hybrid verification platform, which it said can shave months off design time. The platform acts like a bridge between emulation, FPGA prototyping, simulation, static and formal verification and debug. Mentor Graphics uncorked a new version of its embedded hypervisor, which includes better system configuration, debugging and hardware support. The hypervisor is aim... » read more

How To Cut Verification Costs For IoT
By Brian Bailey - 25 Sep, 2014 - Comments: 0

Cost is one of the main factors limiting proliferation of the [getkc id="76" comment="Internet of Things"] (IoT), and when looking at the design and [getkc id="10" kc_name="Verification"] methodologies in place today, verification is a prime candidate for closer inspection. For today’s complex [getkc id="81" kc_name="SoCs"], the cost of verification has been rising faster than design and it h... » read more

Challenges Increase for IP At Advanced Nodes
By Ann Mutschler - 25 Sep, 2014 - Comments: 1

At advanced process nodes such as 16/14/10nm, designing [getkc id="43" comment="IP"] is a much tougher nut to crack due to complexity and other considerations, not to mention then trying to migrate and/or re-use that IP. Still, engineering teams are looking for leverage wherever they can find it in their designs amid the technical challenges to overcome. Tomasz Wojcicki, vice president of c... » read more

IoT Demands Correct By Construction Assembly
By Brian Bailey - 25 Sep, 2014 - Comments: 0

The article Limiters To The Internet Of Things outlined several factors that are slowing the rate of deployment for the [getkc id="76" kc_name="IoT"]. Those limiters are cost, power delivery and storage, standards, security, and the limits of your imagination. This article picks up on a comment made by [getperson id="11244" comment="Chris Rowen"], fellow at [getentity id="22032" e_name="Cadence... » read more

Productivity And The IoT
By Ann Mutschler - 25 Sep, 2014 - Comments: 0

The market for devices that connect almost everything to the [getkc id="76" comment="Internet of Things"] is projected to explode, creating opportunities for companies that haven’t been traditional chip developers to decide to start developing devices. Semiconductor Engineering sat down to discuss this topic with Jack Guedj, corporate VP of Tensilica products at [getentity id="22032" e_name="... » read more

Time To Market Concerns Worsen
By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Leveraging Virtual Prototypes For Hybrid Emulation
By Tom De Schutter - 25 Sep, 2014 - Comments: 0

As highlighted in many of my blog posts, virtual prototyping has really established itself as the key methodology to shift left software development by decoupling the dependency of software development from hardware availability. The success of the “Better Software. Faster!” book illustrates the wide spread interest in the methodology. The success of virtual prototypes also has led users... » read more

High Throughput GSPS Signal Processing For FPGAs And ASICs Using Synthesizable IP Cores
By Synopsys - 24 Sep, 2014 - Comments: 0

This whitepaper illustrates how parallel processing synthesizable [getkc id="43" comment="IP"] cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or r... » read more

Blog Review: Sept. 24
By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

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