tag: Synopsys

The Week In Review: Design
By Ed Sperling - 10 Oct, 2014 - Comments: 0

IP Synopsys rolled out verification IP for mobile PCIe, including built-in M-PHY, for UVM environments. Cadence introduced MIPI SoundWire controller IP, which allows bi-directional digital communication using low gate count and minimal complexity. Deals ARM and TSMC rolled out a road map for 64-bit ARM-based processors at 10nm. The companies said the early pathfinding work is expected t... » read more

Software Before Hardware?
By Ed Sperling - 09 Oct, 2014 - Comments: 0

The emphasis on battery life in wearable electronics, including always-on sensors, and the cost of powering and cooling racks of servers inside of data centers, are beginning to impact the formula for designing systems. Power is now a critical design element, but it's also one of the most stubborn to tackle. While ASICs, SoCs and FPGAs all have focused on being able to efficiently run softwa... » read more

Optimizing Analog For Power At Advanced Nodes
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Memory VIP
By Neill Mullinger - 09 Oct, 2014 - Comments: 0

As the consumer market, and the mobile segment in particular, continues to demand more features and more performance in their gadgets, the designer community is confronted with myriad challenges of delivering on those demands – not the least of which is verifying compliance of ever-evolving protocols that enable the connection of everything within the system on chip (SoC), and the connection ... » read more

Memory Directions Uncertain
By Brian Bailey - 09 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down with a panel of experts to find out what is happening in world of memories. Taking part in the discussion are [getperson id="11073" comment="Charlie Cheng"], chief executive officer at [getentity id="22135" e_name="Kilopass Technology"]; Navraj Nandra, senior director of marketing for Analog/Mixed signal IP, embedded memories and logic libraries at [getentity ... » read more

Energy Boost For Power Standards
By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

Blog Review: Oct. 8
By Ed Sperling - 08 Oct, 2014 - Comments: 0

Mentor's Robin Bornoff examines the thickness of leg hair and just how much of a drag it causes for bicyclists. More hair equals more drag, and thicker hair is worse. Ansys' Justin Nescott routes out the top five engineering articles of the week. Of particular note: The world's most precise clock, which loses one second every 13.8 billion years. Cadence's Richard Goering puts some conte... » read more

Meeting The USB IP Requirements Of SoC Designs From 180-nm To 14/16nm FinFET
By Synopsys - 08 Oct, 2014 - Comments: 0

The ubiquitous USB standard provides data and charging capabilities to a multitude of consumer and enterprise products. USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper ad... » read more

More Than Moore
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Blog Review: Oct. 1
By Ed Sperling - 01 Oct, 2014 - Comments: 0

Cadence's Richard Goering writes about a pair of IEEE working groups that are focused on standardizing ways to lower power of software and firmware. The importance of this effort is huge. Mentor's J. VanDomelen looks at the use of 3D printers in outer space. This is a new chapter in manufacturing custom parts in extreme environments. Synopsys' Mick Posner gets an unexpected answer to a ro... » read more

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