tag: Synopsys

Are Processors Running Out Of Steam?
By Ed Sperling - 14 Feb, 2014 - Comments: 4

In 2004, Intel introduced a new line of Pentium chips that ran at 3.6GHz. Fast forward to today, and the company’s i7 processors run at 3.5GHz with a Turbo Boost to 3.9GHz. There have been many improvements in the meantime. There is more cache and dramatically faster access to data stored in that cache. And there are more cores with improved coherency between them. But the big problem is p... » read more

The Week In Review: System-Level Design
By Ed Sperling - 14 Feb, 2014 - Comments: 0

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

It’s Never Too Early
By David Hsu - 13 Feb, 2014 - Comments: 0

My previous postings discussed the importance of native low-power capabilities and coverage in simulation flows. The complement to this is incorporating complete and thorough low power checking throughout the design and implementation flow, and find and fix as many low-power bugs as possible before simulation. With the right checking tools and proper deployment, doing so enables the possibility... » read more

Do Chips Really Work The First Time?
By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

SoC Integration Mistakes
By Ed Sperling - 13 Feb, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss integration challenges with Ruggero Castagnetti, distinguished engineer at LSI; Rob Aitken, an ARM fellow; Robert Lefferts, director of engineering in Synopsys’ Solutions Group; Bernard Murphy, chief technology officer at Atrenta; and Luigi Capodieci, R&D fellow at GlobalFoundries. What follows are excerpts of that roundtable discussion. SE... » read more

Hardware-Software Rift Persists
By Brian Bailey - 13 Feb, 2014 - Comments: 0

Last month Semiconductor Engineering published an article about power optimization and the roles of the hardware and software teams in reducing energy consumption. The article portrayed the hardware team adding lots of capabilities for power reduction, while the software team was not making full use of those capabilities. That article made the rounds in a couple of LinkedIn forums populated ... » read more

Blog Review: Feb. 12
By Ed Sperling - 12 Feb, 2014 - Comments: 0

Mentor’s Colin Walls adds his perspective to a recent survey by Jim Turley, asking which part of the embedded system development process engineers would rather not change. The choices were the chip, the OS and the tools. Any guesses as to the winner? Cadence’s Richard Goering conducts an interview based on a new branch of circular logic—the CERN supercollider where the Higgs Boson was... » read more

Reduce Power, Area And Routing Congestion
By Various Writers - 12 Feb, 2014 - Comments: 0

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM® AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to... » read more

Cadence To Buy Forte
By The SE Staff - 05 Feb, 2014 - Comments: 2

Cadence agreed to buy Forte Design Systems for an undisclosed sum, enhancing its footprint in the high-level synthesis market as higher levels of abstraction gain traction across the SoC world. For the better part of a decade high-level synthesis (HLS) has been a market opportunity that was just around the next bend, along with electronic system-level design and SystemC modeling. Mentor Grap... » read more

Blog Review: Feb. 5
By Ed Sperling - 05 Feb, 2014 - Comments: 0

Mentor’s J. VanDomelen notes that the Mars colonization selection process has begun, with the actual colonization scheduled to begin in 2025. Remember to bring your own air, water, food, a sewing kit, and lots of reading material. You also may need leg weights for bone density maintenance. What happens if you build a processor using memory as the starting point? Cadence’s Richard Goerin... » read more

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