Fab tools are being fine-tuned for TSV processes as demand ramps for everything from HBM to integrated RF, power, and MEMS in 3D packaging.
From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible.
Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology accomplishes all this in thinner, smaller modules for mobile, AR/VR, biomedical and wearable markets.
Perhaps the most widely recognized use of TSVs is in high-bandwidth memory, where increasingly higher stacks of DRAM chiplets transfer data faster using less power in a smaller form factor than DDR5 memory. TSVs were first employed in CMOS image sensors, but they also enable logic integration with microelectrical mechanical systems (MEMS), RF systems, and the emerging backside power approach for logic devices, which connects power through a thin silicon substrate to the frontside CMOS transistors. The size of the TSVs vary depending on the application, from tens to hundreds of micrometers for CMOS image sensors, tens of micrometers for silicon interposers, and sub-5nm for backside power delivery.
Fig. 1: TSVs range in size from µm to nm diameters and a wide range of depths. Source: imec
Despite decades of fabricating TSVs, the high cost of these process flows limits the wider proliferation of TSVs beyond the established applications. And as the vias become narrower and deeper, the cost of fabrication increases because deeper trenches take longer to etch, continuous liners and barrier metals are tougher to deposit, and copper plating must be more precisely controlled to ensure reliable connections. As such, the equipment and materials suppliers are keenly focused on producing consistent, reliable TSVs for a variety of applications while driving down cost.
A key process consideration is the mechanical and thermal stresses that TSVs exert on the immediate surrounding area. The greater the aspect ratio of the via (feature depth to diameter), the greater the tensile stress induced by fab processes on the surrounding silicon, which can influence carrier mobility and therefore switching speed of transistors. This is the reason why engineers talk about the so-called ‘keep-out zone,’ a surrounding perimeter that must be free of any active circuits. Unfortunately, in the face of escalating I/O counts and finer pitch between TSVs, the desired keep-out zones keep shrinking. To some extent, chip layouts are being optimized for TSV placement from a system level (system-level co-optimization) so that precious silicon real estate can be more productively utilized. Engineers also are exploring the causes of the TSV proximity effect, which helps minimize the size of this buffer zone.
“The interposer is made of silicon, and the TSV is filled with copper, so you have a differential expansion between the TSV and the interposer, said Marc Swinnen, director of product marketing at Ansys. “That means the distribution of your TSVs will determine how the thing warps. Ideally, you would like to spread these TSVs in a perfect grid so the stress is equally separated everywhere, but that’s not the way that TSVs are placed. They’re placed for the connectivity, which means you have clusters of TSVs, and then some voids. So TSV distribution is going to give you asymmetric stresses from place to place.”
To test whether closely spaced TSVs create stresses that affect long-term reliability, Masaki Haneda and colleagues at Sony recently measured the TSV proximity effect in three-wafer stacks with 6µm pitch TSVs and1µm copper-copper hybrid bonded connections.[1] “Especially in order to layout TSVs densely and in finer pitch, understanding TSVs proximity effects is important to minimize the keep-out-zone for device placement,” according to the researchers. They placed silicon-well resistors close to the TSVs on wafer two, because resistors are sensitive to silicon TSV proximity effects. In this case, high reliability was ensured after testing for stress-induced voiding and time-dependent dielectric breakdown (TDDB) of the oxide in the TSVs.
The sensitivity of TSVs to reliability issues is largely attributed to processing issues. Like their much smaller BEOL copper interconnect counterparts, all steps involved in TSV fabrication depend on good results from previous processes. “Poorly filled TSVs, such as underfilling or filled vias with voids, can lead to yield loss,” said CheePing Lee, technical director, Advanced Packaging at Lam Research. “Poor filling is a challenging issue and can be attributed to multiple factors such as poor incoming wafer quality (non-continuous seed coverage before plating), or electroplating equipment or chemistry issues.”
How TSVs are made
Plating is just one step in the TSV process. It takes a total of five process steps to fabricate TSVs. First, lithography patterning defines the trench features, followed by a reactive ion etch (RIE) step that creates an anisotropic (mostly uni-directional) trench in the silicon substrate. Next, a thin SiO2 liner is deposited along the sidewalls to shield the silicon from copper contamination. Then a barrier metal, such as TaN or TiN, is conformally deposited using PVD, long-throw PVD, or possibly atomic layer deposition (ALD), along the via sides and bottom. Then, copper fills the gap fully using electrochemical deposition (ECD), also known as electroplating. Finally, the copper overburden on the top is polished down using chemical-mechanical planarization (CMP).
It’s important to note that conductors other than copper can be used in TSVs, depending on the application. Polysilicon fill often is used for MEMS, and tungsten fill may be used for backside power delivery connection to the standard cell.
The reactive ion etching (RIE) for silicon follows the Bosch method, where etching (using SF6 gas) is rapidly switched to passivation (C4F8) in multiple repeating cycles. This switching between etching and deposition creates a scalloped profile along the trench. The RIE process must be fully optimized to create smooth vias that achieve the desired metal step coverage and low overall resistance. Faster switching between deposition and etch can speed up the process.
The liner oxide generally is deposited using plasma-enhanced CVD. In addition, wet cleaning steps are used throughout the TSV build to ensure any process residue and particles are removed prior to the next process step.
Importantly, the TSV flow may be inserted before any active devices are fabricated, which is called via-first processing. Via-middle involves TSV processing after the front-end devices exist (front end of line) but before contacts and metal interconnects are formed (back end of line). The third possibility, via-last, takes place after some or all of the back-end interconnects are in place.
CMOS image sensors were one of the first applications to use TSVs, and they follow a via-last approach. The TSV flow takes place on the wafer backside after the various wafers are joined using wafer-to-wafer hybrid bonding. Via-first TSVs are used for silicon interposers, whereas via-middle or via-last approaches are being developed for the emerging 3D-IC market.
Multiple types of defects can form during any of the TSV process steps, which include lithography, deep reactive ion etching (DRIE), oxide liner deposition, barrier metal deposition, copper seed, copper electrochemical deposition (plating), and CMP. Following plating, any voids in the copper can result in elevated electrical resistance, decreased mechanical strength, or even device failure. Other prominent defects to watch out for include pattern misalignment, non-uniform deposition, and incomplete filling, which can degrade performance or turn into a long-term reliability risk.
As TSVs scale smaller, the thin barrier metal still needs to provide conformal deposition and ALD is considered an alternative although low throughput in volume production has so far kept more established deposition tools in the process flow. “Atomic layer deposition is a well-known technology, but the challenge lies in bringing ALD into a high-volume environment,” said Patrick Lord, executive vice president of the Customer Support Business Group and Global Operations at Lam Research, in a recent presentation. “As the dimensions keep shrinking, the number of contacts and the contact resistance continues to go up. Enhancements to the ALD process allow us to maximize the area of the conducting material to minimize the resistance. The challenge is to do it productively.”
But not every application pushes TSV processes to the limit. Consider the 8-, 12-, and 16-layer DRAM stacks employing TSVs, which are connected using microbumps on each side of the thinned silicon wafers. “For HBM, TSVs have become smaller but also shallower. The aspect ratio has remained around 10:1,” said Lee. “Currently, the focus is on improving the productivity of the equipment involved in TSV formation because TSV fabrication is expensive — for example, etching faster while keeping uniform via depth and profile throughout the wafer.”
Providers of electroplating platforms seek to rapidly fill TSV trenches across wafers, and from wafer-to-wafer consistently. This process optimization requires close cooperation between tool makers and materials suppliers to develop exclusive TSV plating chemistries that are precisely managed in the plating bath. Plating chemistries include levelers that improve adhesion and facilitate the filling of smaller trenches.
The goal of TSV flows is to create low stress, void-free TSVs on a consistent basis. TSV technology enables high-density vertical interconnection from chip-to-chip, which significantly reduces the three-dimensional size of the end device. The shorter interconnect lengths compared to long wire bonds also lower the device’s power consumption, improves data propagation speed, and improves reliability of the system. This is why TSV technology is crucial to the success of 3D technologies.
The TSV flow additionally needs to be tightly integrated with the subsequent solder bumps, microbumps or hybrid bonded interconnects. Both mechanical and electrical factors come into play. Critical parameters for microbumps include excellent electrical resistivity at the TSV/bump/PCB interfaces, consistent bump height (coplanarity), no partial or fully damaged bumps, no shorting between bumps, etc.
From an overall system viewpoint, is will take time for the industry to make its way from the high-end applications such as SRAM on HPC integrated with high bandwidth memory to the integration of multiple devices with different functions such as photonic ICs, logic and memory, RF and mmWave, capacitors, etc. Modeling of systems at the package level is already underway, which assists in the building of valuable prototypes to help comprehend the various 3D integration issues and how they affect system performance and reliability.
“Virtual fabrication in package assembly enables companies to assess the impact of design changes on manufacturing processes before physical prototypes are even created,” said Mike Kelly, vice president of chiplets and flip chip BGA packaging development and integration at Amkor. “This not only accelerates the product development cycle but also minimizes the risk of costly errors.”
Emergence of the nSV
Backside power delivery is a novel approach being developed by the top three foundries for 2nm node devices. By segregating power from signal lines in advanced logic chips with perhaps 15 layers of copper interconnects, backside power distribution can reduce power losses by up to 30% by driving down voltage droop and RC delays.
There are at least three approaches to backside power delivery, each with increasing levels of process complexity, but offering better scaling and performance benefits. In the most aggressive form, the nanoTSVs are created between the fins before the devices are fabricated (via first). The least aggressive form runs the power line up and over the already fabricated devices (via middle).
“The first approach is a kind of a TSV or contact that you do from the front side to the backside.
So you can think of different ways, but it’s inevitable that you need to have the 3D space to make that contact hole,” explained Eric Beyne, senior fellow, vice president of R&D, and program director for 3D system integration at imec. “It sits where you normally have the Vdd and Vss boundaries of the standard cells. That’s where the so-called backside TSV comes in.”
This metal contact can be created from the front side of the wafer, and then the silicon is polished back to expose the contact. Alternatively, the process can proceed from the backside of the wafer with polishing on the front side. “Or you could do something in between, like we’ve shown with a nanoTSV landing on a buried power rail,” said Beyne.
Fig. 2: Front-side power delivery network (left) to backside power delivery network (middle) to BSPDN with nTSV. Source: imec
Imec recently presented different integration schemes [2], for which Beyne and colleagues demonstrated nTSV first and nTSV last flows. The processes involves advanced backside grinding down of the silicon to 5µm thickness (finally hundreds of nm), wafer-to-wafer bonding, and lithography correction to account for distortion caused by the thermal processes of fabrication and bonding. The resulting nTSV size is in the sub-1µm range with 5µm depths.
Another concern is the increased resistance of fine pitch metal layers, which increases the use of routing resources in the BEOL to deliver power with a low impedance. This places additional constraints on place-and-route efficiency of EDA tools.
Conclusion
The emergence of the chiplet concept and growing applications for 3D integration has brought great attention to through-silicon via technology. TSVs play a crucial role in silicon interposers and three-dimensional (3D) heterogeneous integration schemes. As the interconnect integration density continues to increase, the metal filling of TSVs with small critical dimensions (CDs) and high aspect ratios (ARs) becomes more and more challenging and expensive. Therefore, there is a growing trend to investigate high-quality and lower-cost approaches to creating and filling smaller and deeper TSVs while ensuring excellent connection with other chips, whether they are connected to bumps, microbumps or hybrid bonds.
Toolmakers and material suppliers will continue to develop next-generation TSV solutions for interconnected 3D packages, and eventually, 3D-ICs.
References
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