DSA, Multi-beam Make Steady Progress

Semiconductor Engineering sat down to discuss current and future lithography challenges with Laurent Pain, lithography lab manager at CEA-Leti. What follows are excerpts of that conversation.

SE: CEA-Leti has two major programs in lithography. One is in directed self-assembly (DSA) and the other is in multi-beam e-beam. Let’s start with multi-beam. What is Leti doing in multi-beam and what is the Imagine program all about?
Pain: Leti has a long history in electron-beam direct-write lithography and the integration demonstration of this technology to support CMOS manufacturing. Leti is currently evaluating and pushing for the insertion of this lithography concept around the Imagine program. This is centered around Mapper Lithography’s multi-beam e-beam platform. Four years ago, Leti initiated a collaborative program to help accelerate this massively parallel electron-beam approach. Imagine addresses the tool assessment of Mapper’s platform. It also addresses resist processes, data treatment, outgassing and optic contamination. Our partners include TSMC, ST, Canon, TEL, DNS, TOK, JSR, Dow, Nissan Chemical, Aselta Nanographics and Mentor Graphics. We are also in discussions with some new prospects.

SE: Isn’t Leti also involved with the eBeam Initiative?
Pain: Leti has a lot of expertise in e-beam lithography and has demonstrated its ability to fulfill the CMOS manufacturing requirements in a real fab environment. From this background and its own initiative in ML2, Leti is a sponsor of the policy developed by the eBeam Initiative for the promotion and the acceptance of e-beam technology by the industry. As an active member, Leti participates to demonstrate the attractiveness of EBDW.

SE: What is the status with the multi-beam tool from Mapper? Has Leti installed the system yet?
Pain: A prototype platform has been in operation inside Leti’s premises since 2009. It has demonstrated 18nm half-pitch resolution capability. We are very close to 16nm half-pitch. The pre-production platform is under installation with first exposures targeted at the beginning of 2014.

SE: Mapper originally promised to ship a multi-beam tool with 13,000 beams by now, but the development of the system has been far more complicated than previously thought. So now, the first machine from Mapper will consist of only 1,300 beams, right?
Pain: Yes. The first exposures are scheduled for the beginning of 2014. Then, we plan to ramp up the tool. The initial target is 32nm half-pitch with one wafer per hour (wph) throughput in 2014. In effect, ML2 technology is transitioning from R&D to pilot line. 2014 will be the crucial year with a demo target of full field exposure, alignment capability and a one wph throughput. This is greater than 100x of present single e-beam technology.

SE: The eventual goal is still to develop a Mapper tool with 13,000 beams, right?
Pain: The final target of 10 wafers per hour throughput with the 13,000 beam tool is scheduled for 2015. So, the initial target is 32nm half-pitch at one wph throughput in 2014, and a final target of 10 wph in 2015.

SE: We’ve seen several delays for multi-beam. In general, when do you see multi-beam finally going into production and at what node?
Pain: The time-to-qualify and the ramp up for the technology is about mid-2015, most likely for the one wph system. In the meantime, a 10 wph prototype will be under qualification. This first system will more likely be used for low-volume production and will address not only advanced nodes to overcome the cost issues of multi-patterning, but also less advanced nodes with a throughput capability going from two to five wafers per hour. Finally, for fast prototyping and faster cycle time, the introduction of such a tool could give chipmakers a substantial competitive advantage.

SE: What are the applications for multi-beam?
Pain: Contact and via levels should be the first targets. Eventually, we see all levels, where you can avoid triple- and double-patterning.

SE: What do you see as the biggest challenge in order to bring multi-beam e-beam into mass production?
Pain: Basically, no technical showstopper is foreseen for the moment at the module level. The main risks include full system integration and the timing based on the ramp-up speed of this future tool. Industry acceptance is also key. And despite the interest level, there are still technical and political issues to overcome. A broader acceptance of the technology, of course, will speed up the ramp of the technology.

SE: Are there any challenges for multi-beam in terms of resists, mask data preparation and other infrastructure issues?
Pain: The resist technology is well aligned in terms of intrinsic performance (i.e. resolution, LER) with EUV. Concerning the sensitivity, it is on target with an acceptable throughput. In mask data preparation, there is good support from EDA vendors, and we don’t anticipate any difficulties to have the data infrastructure ready.

SE: Does multi-beam have any advantages over extreme ultraviolet (EUV) lithography?
Pain: The main advantages of ML2 over EUV are the tool cost and there is no need for a mask. ML2 technology should reduce the cost of ownership for end users that adopt it. EUV today suffers primarily from source power capabilities that impact the throughput. ML2 will again require time before demonstrating full throughput capability at the manufacturing level. EUV today has demonstrated better lithography on a pre-production tool. This level is expected to be reached on ML2 starting 2014. Nevertheless, we feel both technologies could be adopted, with EUV for very high volume production and ML2 for low-to-mid volume production.

SE: Besides TSMC and perhaps STMicroelectronics, there has been lackluster support in the industry for multi-beam. Is multi-beam seeing more support from the industry now?
Pain: Major IDMs are still looking closely at ML2 and claim that they will finalize their decisions once technology capability is demonstrated and the timing is right. Interest is shifting and increasing among a second wave of IDMs, which are looking for the opportunity to access the technology. ML2 offers the possibility to address medium- to high-end nodes with the same platform and the same infrastructure requirements at lower costs.

SE: Let’s move to DSA. What is Leti doing in DSA?
Pain: Through a partnership with the French polymer manufacturer Arkema, Leti is working on the introduction of DSA technology for manufacturing. For this, Leti has established a joint collaborative program named Ideal. The partners for Ideal are Arkema, DNS, TEL, ST, TOK, ASML, Mentor Graphics and CNRS French labs LTM and LCPO. The aim is to develop a materials platform using PS-PMMA and high chi polymers, which are compatible with CMOS manufacturing requirements in term of supply and specifications. The other goal is to demonstrate Arkema’s block copolymer materials within Leti’s 300mm DSA pilot line. We not only want to integrate the materials and technology into a standard CMOS flow, but also to develop a design and equipment infrastructure.

SE: What have you demonstrated with DSA?
Pain: Arkema is now reaching the point of being ready to supply PS-PMMA materials in volume and with specifications required by the industry to start implementation. Leti has implemented those materials in its 300mm pilot line and achieved resolutions down to 10nm half-pitch, with excellent CD control and edge roughness after pattern transfer. Integration work on a real test case is ongoing. The first proof of a new generation of high chi materials for the sub-10nm node has been achieved. The work is dedicated for use in contacts and vias, with an application for contact shrinks and multiplication.

SE: Where does DSA fit in lithography? What about yield or defects with DSA?
Pain: DSA technology is a good fit for contact/via patterning for BEOL applications. The second application is for line and spaces in finFet/nanowire levels. Defectivity could be the one showstopper of the technology. This is one of the key focus studies of Leti’s work with Arkema’s materials. We are generating data for our partners and the initial trends look promising. But that needs to be confirmed in demonstrations and under processing.

SE: Finally, when do you think DSA will move into production?
Pain: This is a good question. If we confirm a good defectivity trend, I will not be surprised to see the introduction starting somewhere in 2015 to 2016, probably for memory applications first with PS-PMMA material. Today, a lot of active programs are running directly in the fab environment. This technology provides promising potential both in terms of resolution and cost. For line and space applications, the probable insertion point is for sub-10nm nodes with high chi block copolymers.