Tooling challenges increase as advanced packaging ramps up.
The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp.
Applied Materials recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging.
ECD—sometimes referred to as plating or electroplating—is used in the manufacturing of packages, such as 2.5D/3D, BGAs, CSPs and wafer-level packages. In one common application, ECD is used to deposit the copper metallization schemes in IC packages, enabling the electrical connections within the structure. In addition, ECD can deposit other metal types, such as gold, nickel, palladium, silver and tin.
More specifically, ECD is used to deposit metals in the key interconnect structures within an IC package, such as bumps, copper pillars, redistribution layers (RDLs) and through-silicon vias (TSVs). Each of these interconnect structures are used for a particular package type. And each one has a number of different challenges in the ECD process.
“[The processes] are determined by the different types of packaging capabilities,” said Robert Betts, global product manager at Applied Materials. “The number of metal layers increases with the complexity of the packaging technique. From an industry standpoint, the number of ECD layers will continue to grow as the complexity grows within the wafer-level packaging (and other) arenas.”
ECD is challenging, though. The problem is how to deposit uniform and void-free metals at reasonable speeds for the next wave of IC packages. Tool flexibility, uptime and cost-of-ownership are also critical.
What is ECD?
In total, the ECD equipment market for packaging alone is roughly a $300 million to $500 million business, according to analysts. Applied Materials is the leader in this sector, followed by Lam Research and TEL, according to analysts.
Atotech, Ebara and EEJA also compete in the ECD equipment market for packaging. Then, ClassOne Technology and others compete for the ECD business at 200mm wafer sizes and below.
ECD is not a new technology. For years, it has been used in both the wafer fab and by OSATs. In the fab, it is used to deposit the copper metallization for the tiny interconnects in the metal layers of a chip. ECD also provides the copper metallization and other metals in IC packages.
Regardless of where it is used, the principles are the same for ECD. Basically, a wafer enters a multi-chamber ECD tool and the substrate is dipped in an electrolyte bath. Then, when a current is applied, metals are deposited on select regions of the wafer. ECD can be used to deposit various metals, depending on the application.
“It’s a voltage that creates current, which results in the deposition of metal. And the voltage that you operate at determines which species are deposited,” said Kevin Witt, president of ClassOne Technology, a supplier of ECD tools and other equipment. ClassOne Technology is a sister company of ClassOne Equipment, a supplier of refurbished tools.
Another tool technology, physical vapor deposition (PVD) or sputtering, can perform many of the same functions as ECD in packaging. In PVD, atoms are ejected from a target and then deposited on a surface.
“The deposition rates of ECD are much faster than sputtering. In some cases, you can plate multiple microns a minute, maybe three, five, six, seven or eight microns a minute of different metals,” Witt said. “So the minute you start talking about thick films, meaning anything over a half-micron, the cost-of-ownership for plating is an order of magnitude less than an equivalent sputtering process.”
Today, traditional wirebond packages still make up more than 80% of the overall chip packaging market. Developed in the 1950s, wire bonding is a fast and cheap solid-state welding process. Using a wire bonder, chips are stacked and then stitched together with tiny wires.
For processors and other devices, though, wirebond doesn’t provide enough I/Os. So in the 1960s, IBM developed a technology called flip-chip. Flip-chip actually is an interconnect scheme rather than a packaging type. It’s a way to provide the interconnects from one die to another die or a die to a board.
Today, flip-chip is still used to make several lower-cost package types, such as ball-grid array (BGA) and chip-scale packages (CSPs). “Some are looking for a low-cost packaging solution,” Applied’s Betts said. “Typically, flip-chip is used in this low-cost arena.”
In a simplified flip-chip flow, a chip is fabricated in the fab. Then, a sea of tiny bumps is formed on top of the chip. The device is flipped and mounted on a separate die or board. The die or board consists of copper pads. The bumps land on the copper pads, thereby forming an electrical connection.
In flip-chip, there are several ways to make bumps. In one flow, a surface is deposited with an under-bump metallurgy (UBM) material, or seed layer. Then, the dimensions of the bump are defined. A resist is applied on the surface and then removed, forming a small gap.
Following that step, an ECD tool deposits a layer of copper or other metal on the UBM. The copper ions move on the regions covered by the seed layers.
Then, the ECD tool deposits a nickel layer, followed by a lead-free tin-silver (SnAg) compound. The nickel layer acts as a diffusion barrier between the copper and SnAg material. Finally, the SnAg material is reflowed or heated into a bump or solder ball, which serves as the connection from the die to the board.
Copper is a low resistivity material, making it ideal for the interconnect. At one time, the industry used lead for the bump or solder ball. But several years ago, it moved away from lead due to environmental factors. “The move away from lead brought us to lead-free tin-silver,” Applied’s Betts said. “Typically, it’s a mix of 3% silver or less in regards to tin-silver plating.”
In today’s devices, the bumps are 60 to 100μm high and 80-125μm in diameter, according to Amkor. The uniformities of the bumps are critical. If they are not uniform, the package could encounter some reliability issues.
This technology is limited, however. So starting at 65nm, Intel and others moved from traditional bumps to a technology called copper pillars for its microprocessor lines. Like bumps, copper pillars are not a packaging type. Instead, they serve as an interconnect between two dies or a die to a board.
Copper pillars enable more I/Os, smaller pitches and better thermal conductivity, compared to traditional solutions. “Traditional bumps use certain solder alloys and collapse during solder reflow, while copper pillars with tin-silver caps retain their stand-off height,” said Nokibul Islam, deputy director of product technology marketing at STATS ChipPAC. “Traditional solder bumps are not scalable to very fine pitches, while bump density can be significantly increased with copper pillars. There is a certain bump diameter required for traditional bumps to be plated, whereas copper pillars can be plated as small as 10μm to 20μm in diameter.”
Today, logic, memory and 2.5D/3D devices are housed in packages using copper pillars. “The sweet spots we see (for copper pillars) are in fine-pitch applications in the mobile and consumer markets, where you can shrink your die size and increase performance by using fine-pitch copper pillar technology,” Islam said.
“Copper pillar is now the mainstream interconnection for flip-chip, but it has not completely displaced standard lead-free bumps,” he said. “In terms of production volume, approximately 65% to 70% of flip-chip packages utilize copper pillar and the balance is lead-free bump and other types of bumps. Based on the current industry trend, it will likely take another four to five years for copper pillar to completely displace lead-free bumps.”
Meanwhile, in some cases, the copper pillar manufacturing process resembles a bump flow. For example, a seed layer is deposited on the surface. Using ECD, a copper layer is plated over the seed layer, followed by a nickel diffusion barrier and a SnAg solder cap.
Then, the pillars are surrounded by an underfill material and then encapsulated to protect the structure. “The copper pillar structure also helps to maintain a very good stand-off height, and hence will enhance the capillary underfill/molded, underfill process window,” Islam said. “Typically, though, copper pillar bump is much stiffer than standard solder bump, which creates much higher stress in the die during the flip-chip attach process. To minimize stress (for the low-k dielectrics), a robust flip-chip process for copper pillar is required to protect the fragile die.”
There are other issues as well. “The extreme low-k or ultra low-k (ELK/ULK) interlayer dielectric (ILD) materials used in conjunction with advanced silicon nodes and bigger die sizes are more fragile and susceptible to cracking or delamination during the flip chip assembly process,” he said.
Indeed, copper pillar technology is more complex than traditional bumps. For example, the dimensions are smaller, as copper pillars are moving from 50 to 100μm in diameter today to 10 to 30μm in the future, according to Dow Electronic Materials.
Depending on the requirements, the pillars might be tall, short or thick, and may have a flat top or a dome shape. Regardless, the pillars must be uniform and consist of a within-die (WID) uniformity of less than 5%, according to Dow. If there is variation in the pillar structures, the package may encounter some reliability issues.
“The key requirements for copper pillars are the thickness uniformity and the pillar shape,” said Wataru Tachikawa, global marketing manager for advanced packaging metallization at Dow Electronic Materials. “From the plating side, the thickness uniformity control is difficult. Typically, copper pillar requires a relatively high plating thickness. Plating speed is also important.”
In the flow, it could take seven to eight minutes to fill or plate a copper pillar, Dow notes. Obviously, OSATs want faster ECD tools, but faster plating has some drawbacks as it can cause unwanted voids in the pillars, as well as other problems. “If we increase the plating speed, the thickness uniformity can become worse,” Tachikawa said. “So you have plating speed and thickness uniformity. The balance of those two is a very challenging area for this application.”
There are other challenges. “It is also important to minimize within-feature shape variations and within-wafer uniformity during the plating process step to achieve good wafer bumping yields,” said Boaz Kenane, vice present and general manager for packaging ECD at Lam Research. “Furthermore, interactions between the different metals that incorporate bumps—such as copper, nickel, tin and silver—could cause integration defects if not handled carefully by the right chemistry selection and the right plating method tailored on the ECD tools.”
Besides copper pillars, electroplating also plays a big role in the development of fan-out packages. In fan-outs, the interconnects are fanned out in the package, enabling more I/Os.
The illustration above is a concept of a multi-level fan-out package. In this example, two separate fan-out packages are stacked and soldered together to form a fan-out package-on-package (PoP).
The fan-out package has several key parts, including mega-pillars and RDLs. The two mega-pillars connect the lower and upper packages in the fan-out PoP. The thick mega-pillar structure is roughly 200µm. For this, the uniformity needs to be less than 10%. “Because this involves thick plating, the plating speed is very important,” Dow’s Tachikawa said.
The problem? “These are tall structures and require long plating times,” Lam’s Kenane said. “Hence, a high-rate deposition process is desirable to minimize the overall cost-of-ownership.”
In fan-out, meanwhile, the I/Os of a die are in one location and the bumps may reside in another place. So, the industry uses RDLs or tiny traces, which re-routes the signal path from the die I/O to the bumps. Using ECD, the RDLs are plated with copper.
Today, linewidths of the RDLs are around 10μm. 5μm is considered the leading edge with 2μm in R&D. “Making fine lines like 2µm or 1µm linewidths involves several challenges,” Dow’s Tachikawa said. “One is the thickness uniformity. The cross section of the copper traces becomes very small. The mechanical strength becomes very weak. If there is stress, the copper can easily break or crack. So, having good mechanical properties is one of the key requirements.”
Compounding the problem is that high-density fan-out packages can have three to five RDL layers. “With the move toward smaller line and space requirements, manufacturers are developing various via-RDL plating integration schemes. It is important to minimize variations in via-RDL plating thickness as this could lead to topographical variations, thereby creating certain challenges during the downstream process sequences,” Lam’s Kenane said. “Lastly, it should also be noted that high-density wafer-level packages may be warped as a result of stresses during the multi-layer build-up process. Hence, the capability to handle and process warped wafers (> +/- 5 mm warpage) is an important requirement.”
In another application, the industry continues to ramp up a new wave of 2.5D/3D chips using TSVs, either using a separate die with TSVs in 2.5D or running them through the die in 3D. “We are also witnessing the increased use of through-silicon via solutions for delivering next-generation high-bandwidth memory (HBM) and CMOS image sensor (CIS) devices,” Kenane said.
Plating copper inside the TSVs remains a challenge. “A key requirement here is achieving defect-free, bottoms-up via fill of high aspect ratio (>10:1) structures with often less-than-perfect seed coverage,” Kenane said. “This requires tool and chemistry stability throughout a slow bottoms-up fill process over multiple wafers, which represents a unique challenge.”
Given the challenges, ECD tools must meet certain requirements. “It should also be noted that the ECD process–a critical step for advanced packaging–may also be irreversible (i.e., wafers cannot be re-worked in case of misprocessing). Maintaining a tight control on ECD process uniformity has a crucial role in maintaining overall device yield and minimizing wafer scrap,” he said.
There are other requirements. “Customers want to see a plating system that is advanced and capable of a variety of different packaging scenarios,” Applied’s Betts said. “It’s changing so rapidly that they need a system that is flexible and productive enough to meet their unanticipated as well as anticipated needs.”
In response, Applied Materials recently rolled out its latest ECD tool. The system, dubbed Nokota, is a multi-chamber tool that supports 150mm, 200mm, and 300mm wafer sizes, and handles a range of metals. It has a MTBF of more than 350 hours and lowers the cost of plating.
In operation, a wafer populated with chips is moved into the tool and the substrate is automatically sealed in an assembly unit. The unit transports the wafer through various cells. Each cell performs a variety of ECD steps depending on the recipe.
The seal protects the wafer during the process, thereby preventing leaks in the flow. “Generally, the industry standard is that there is a seal ring, or some type of safe-seal assembly, in each chamber in the system. So the wafer would be chucked or sealed at each plating step before it goes out,” Betts said. “In our case, we are reducing risk and we are increasing wafer protection because we seal the wafer one time.”
Lam, TEL and others also sell high-end ECD tools. Then, ClassOne Technology and others provide ECD tools for smaller customers at wafer sizes at 200mm and below.
“The tools (from the larger companies) are 300mm workhorses,” ClassOne Technology’s Witt said. “What does a guy who does 4-inch wafers do? He only buys one tool because he doesn’t do 5,000 wafers a week.”
For those customers, ClassOne sells “a generic plating tool that can be used for a range of different processes. We can sell a small capacity tool that does the job,” he said.
Smaller customers can be challenging, though. They don’t have large budgets and require a lot of handholding. In contrast, the large OSATs understand the requirements, but they can be demanding, making ECD a challenging business on several levels.
Betting On Wafer-Level Fan-Outs
Chipmakers focus on packaging to reduce routing issues at 10nm, 7nm. Tool and methodology gaps remain.
Making 2.5D, Fan-Outs Cheaper
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.
Packaging Wars Begin
OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.