Issues And Options At 5nm

Lithographers look at the possibilities and challenges three nodes ahead and whether those are even the best options.


While the foundries are ramping up their processes for the 16nm/14nm node, vendors are also busy developing technologies for 10nm and beyond.

In fact, chipmakers are finalizing their 10nm process offerings, but they are still weighing the technology options for 7nm. And if that isn’t enough, IC makers are beginning to look at the options at 5nm and beyond.

Today, chipmakers can see a path to 5nm using traditional CMOS, although 3nm is still too far out in the future. But 5nm is not that far out and is expected to appear in 2019, according to the International Technology Roadmap for Semiconductors (ITRS).

Needless to say, the 5nm roadmap could slip. There are still a multitude of unknowns and challenges at 5nm. And the questions are clear: Will 5nm ever happen? If so, how will chipmakers get there?

As before, chipmakers must depend on lithography for IC scaling, but patterning technology remains in flux. Extreme ultraviolet (EUV) lithography and the other next-generation lithography (NGL) technologies were supposed to propel the IC industry toward the advanced nodes, but most NGLs are delayed and still not ready.

So, chipmakers must continue to extend today’s 193nm immersion with multiple patterning, but the question is when will optical finally run out of steam?

Still, lithographers can’t afford to wait around and are lining up the options for 5nm. “There are a number of options,” said Yan Borodovsky, a senior fellow and director of advanced lithography at Intel. “All of them are doable.”

The options, which could change overnight, include the usual suspects—DSA, EUV, multi-beam, nanoimprint, and 193nm immersion/multi-patterning. It may also require some different approaches, such as high numerical aperture (NA) EUV, and EUV with multiple patterning or DSA.

Selective deposition, a futuristic patterning-like option, also could play a role. “Along with lithography, you will see a lot of innovation in the materials,” said Uday Mitra, vice president and chief technology officer for the Etch Business Unit at Applied Materials. “People are talking about selective deposition, where you start growing things from the bottom up.”

Looking in the crystal ball
Barring a major breakthrough in lithography, chipmakers will use today’s 193nm immersion with multiple patterning for both 16nm/14nm and 10nm. Then, at 7nm, the lithographic roadmap is also fairly straightforward. As it stands today, chipmakers plan to use EUV and/or 193nm immersion with multiple patterning. This, of course, depends on the readiness of EUV.

By 5nm, though, the IC industry could look completely different. For example, today’s finFET transistor is projected to reach its physical limit at 5nm, prompting the need for a next-generation transistor architecture. As before, the leading next-generation transistor candidates are gate-all-around FETs, nanowire FETs, SOI finFETs and tunnel FETs.

And if chipmakers move to a next-generation transistor, the industry will likely require new EDA tools, fab materials and equipment.

Given the monumental and costly changes required for 5nm, there are other scenarios. One possibility is that chipmakers may delay 5nm. Instead of scaling, the industry may opt to develop 2.5D/3D IC chips as a means to circumvent the costs associated with lithography.

“For 5nm, the technology choice is not clear,” said Intel’s Borodovsky. “The design options are not clear as well. We need another two years to pick the best solution.”

The options
In any case, lithographers must prepare ahead of time. So what are the possible options for 5nm? There are still several unknowns, but the optimal scenario is what Borodovsky calls “complementary lithography.”

In this technique, there is a two-step patterning process—lines and cuts. Ideally, 193nm immersion would pattern the lines, while EUV or another NGL would handle the harder part—the cuts.

If NGL remains delayed or fails by 5nm, then the industry may need to extend optical lithography to 5nm. But will it work? In reality, single-exposure, 193nm lithography reached its limit at 40nm half-pitch, but the industry has extended optical by using various resolution enhancement techniques (RETs).

In one possible RET-enabled optical path to 5nm, Tokyo Electron Ltd. (TEL) has demonstrated a self-aligned octuple patterning process that enables 5.5nm features. “We know how to do it, because the tolerance of thin films is much better than that,” Intel’s Borodovsky said. “So, it’s not pitch division that will stop more scaling. But it’s when you have to break those pitches in those lines to provide the electrical functionality. That’s what you have to worry about. You also have to worry about edge placement error.”

At advanced nodes, optical lithography faces other challenges. “We will extend (optical lithography) as far as possible,” said Burn Lin, vice president of research and development at TSMC, “but overlay accuracy is mechanically and metrology limited.”

Octuple patterning itself is daunting. “It’s feasible that you can do it, but there are so many layers,” said Brian Trafas, chief marketing officer at KLA-Tencor. “It’s complex and costly.”

For IC designers, the thought of octuplet patterning is terrifying. In octuplet patterning, at least in theory, the mask layers are assigned eight colors. Then, the mask layers are split, or decomposed, from the original drawn layout into eight new layers.

Using that complicated scheme, only a few chipmakers may be able to afford to design and make chips in the future. “The leading-edge semiconductor business is going to be very different if we have to stick with 193nm immersion. It may limit the availability of the leading-edge nodes to a select few,” said Aki Fujimura, chief executive at D2S. “(That’s why) we are all hoping that EUV is going to happen at 7nm.”

But it’s unclear if EUV will be ready for 7nm amid ongoing delays with the power source. There are other limitations. Using a 13.5nm wavelength, EUV enables resolutions down to 22nm half-pitch. So, to pattern features at both 7nm and 5nm, EUV would require multiple patterning.

“If you bring EUV into the picture, it helps some for 7nm. But it is not a total solution for 7nm,” said Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries. “Even for 5nm at 0.33 NA, EUV is not going to cut it. You need high NA.”

In theory, a high NA lens would improve EUV resolutions. But it may also require the photomask industry to move to a new 9-inch mask size. Today, the standard mask size is 6-inch. Needless to say, the mask industry lacks the resources to move to a new reticle size.

To support 6-inch masks, ASML is proposing an anamorphic lens for EUV. The anamorphic lens would support 0.5 to 0.6 NAs as a mean to boost the resolutions. The two-axis lens would support 8x magnification in the scan mode and 4x in the other direction.

With that solution, however, the EUV scanner could take a throughput hit. It would expose the wafer at only half the field size. And the EUV scanner itself may require a re-design, which could be an expensive proposition.

Meanwhile, two other NGLs—multi-beam e-beam and nanoimprint—still have a way to go before they can enter into the discussions for 5nm.

Directed self-assembly (DSA), however, is a possibility for 7nm and 5nm. Used in conjunction with 193nm immersion or EUV, DSA makes use of block co-polymers to reduce the pitch of the final printed structure.

DSA faces some challenges, namely defectivity. The other problem is design-for-DSA. In one experiment, for example, Samsung assembled more than 1,000 DSA guide patterns in a layout with 27 process corners. “The estimated total verification time easily reached over six months,” said Seong-Bo Shim, a researcher for Samsung.

To reduce those times, Samsung proposed a solution that consists of two parts—modeling and verification. The modeling portion consists of test guide patterning preparation and characterization. This determines whether the guide pattern causes a defect. Then, in the verification process, there is another characterization step. This, in turn, detects a hot spot. “We tried two types of model methods,” he said. “One is cut-line, which shows more accuracy, but it has no extendibility. Another one is the global model. It shows a little lower accuracy but more extendibility.”

Besides the NGLs, there is another emerging option—selective deposition. Still in the R&D stage, selective deposition could be used to selectively deposit materials, namely metals on metals and dielectrics on dielectrics, on a device. “There are a lot of people thinking about this today,” said Girish Dixit, vice president of process applications for Lam Research. “There are many areas that selective deposition could be used in, including doing edges or removing something at the expense of something.”

Selective deposition involves the use of special chemistries and existing atomic layer deposition (ALD) tools. It also makes use of molecular layer deposition (MLD), which is similar to ALD. “With MLD, you are typically making something that is primarily an organic, composed of carbon, nitrogen, oxygen and hydrogen. In classic ALD, you are making inorganic materials. There are also hybrids,” said James Engstrom, a professor in the School of Chemical and Biomolecular Engineering at Cornell University.

There are some differences between traditional ALD and selective deposition using ALD. “The difference is you somehow trick the ALD process, so that it grows on material A, but does not grow on material B,” Engstrom said.

Selective deposition doesn’t replace lithography, but it does solve a problem—edge placement error. “When you want one thing to line up with another, the ability to control the placement of a feature is getting to be outside the range, because the features are small,” said Gregory Parsons, a professor in the College of Engineering at North Carolina State University.

In a theoretical flow, a lithography tool would first pattern a surface. “So, if there is a pattern available on the surface that you want to selectively deposit, then your material that you are forming would then align to the pattern that is underneath the substrate,” Parsons said. “Instead of a physical mask to align, you would want to use the chemistry of the surface to do the alignment. And if the process can recognize that selective chemical difference, then we can deposit materials exactly where we want.”

Still, the technology is unproven and there are challenges. But if the technology works, it could possibly change the landscape in IC manufacturing. “Once the ball is rolling, and you can do selective deposition on anything, then the applications will expand,” Lam’s Dixit added.