Delays at 10nm raise questions about what’s next.
Citing an assortment of undisclosed manufacturing issues, Intel in July pushed out the introduction of its 10nm chip and process technology to the second half of 2017. This is roughly six or more months later than expected.
With the delay at 10nm, Intel also pushed out its process cadence from 2 to 2.5 years. Other foundries, meanwhile, are struggling to keep up with the traditional 2-year process cadence, raising more questions about the future of chip scaling and Moore’s Law.
Indeed, given that the node transitions are slowing, and chip-scaling costs continue to soar, the big question is what will happen to 7nm and 5nm. Or for that matter, will 7nm and 5nm ever happen?
The timing and overall certainty of both 7nm and 5nm remain unclear. But if 7nm and/or 5nm do happen, the technologies will be expensive and limited to a select few with deep pockets. Moreover, a large number of applications will never use it.
Still, there is a market for chips at 7nm and beyond. High-end systems such as servers and networking equipment will continue to consume leading-edge chips, but it’s unclear if these processes will ever migrate beyond those applications.
“7nm will happen,” said Joanne Itow, managing director of manufacturing at Semico Research. “The development will progress on schedule. I don’t believe it will be necessary to release 7nm with that much urgency. There’s no specific product or company that is driving the need to release a 7nm process within 24 months after 10nm. 5nm will also be developed and put into production. What it will look like is still a question mark.”
Behind the scenes, the R&D community remains firmly committed to these technologies. “People are still pushing for 7nm and 5nm,” said Aaron Thean, vice president of process technologies and director of the logic devices R&D program at IMEC. “For us, we are not slowing down. The research can’t slow down. And our partners continue to want us to find a solution to enable scaling. But how things are adopted in the industry and how that translates to products is a very complex problem that relates to business. Cost is the big component in that decision.”
Based on the roadmaps from Imec and its members, chipmakers hope to bring 7nm into early production by 2017, with volume production slated by roughly 2019 to 2020. The 5nm node is still a work in progress, however.
While the production schedules could change over time, the technology roadmaps, and options, also remain in flux. And just by looking at Imec’s roadmap, chipmakers face some tough technology decisions.
For example, in Imec’s previous roadmap from a year ago, there were three transistor candidates for 7nm: gate-all-around nanowire FETs; quantum-well finFETs; and SOI finFETs. Today, in Imec’s most recent roadmap, there are two basic options for 7nm—the finFET and the lateral gate-all-around nanowire FET. Both options could use either bulk CMOS or silicon-on-insulator (SOI) substrates.
The industry currently is leaning toward the finFET at 7nm. Nanowire FETs provide better electrostatics than finFETs, but they are more difficult to make. Basically, the lateral nanowire FET is a finFET with a gate wrapped around it.
Last year, meanwhile, Imec also listed several transistor options at 5nm—III-V finFETs; nanowire FETs; quantum-well finFETs; SOI finFETs; tunnel FETs; and vertical nanowires.
Today, the lateral nanowire FET is the sole option at 5nm, according to Imec. Vertical FETs, TFETs and the other technologies have been pushed out to 3nm.
FinFETs vs. nanowire FETs
Meanwhile, to scale devices down to 7nm and 5nm, the industry will require new tools and materials. For example, chipmakers are begging for extreme ultraviolet (EUV) lithography by 7nm. The industry also wants new selective deposition tools, multi-beam inspection and others.
By then, the industry will need to take a hard look at cost. For 28nm capacity, the cost for 10,000 wafer starts per month (wspm) is under $1 billion. Eventually, for finFETs, the cost per 10,000 wspm will be in the $1.3 billion range, according to Martin Anstice, president and chief executive of Lam Research, at a recent presentation at Imec.
Based on today’s estimates, the cost for 10nm and 7nm will range from $1.5 billion to $2 billion for 10,000 wspm, Anstice said. “In my opinion, that’s not sustainable,” he said during the presentation. “A lot of time and effort will need to be invested to deliver productivity solutions to deal with that problem between now and then.”
Clearly, there are also challenges on the device side. For example, chipmakers must decide to go with either the finFET or the nanowire FET at 7nm.
For many, though, it makes more sense to extend the finFET to 7nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin. “FinFETs, of course, will go as far as they can,” said Terry Hook, a senior technical staff member at IBM Research. “As I see it, the difference between finFETs and the lateral nanowire is electrostatics. And I do not believe that we have exceeded the limit of electrostatic scaling for finFETs at 7nm. Fin width reduction, staying above the serious adverse quantum effects, would suggest that you can get the gate length to approximately the 12nm range, with a fin width of 4nm to 5nm. This may even be sufficient for 5nm node scaling.”
To extend the finFET, though, the device will require several innovations. “Due to contact poly pitch and fin pitch scaling, drive current degrades on 7nm compared to 10nm,” said Srinivasa Banna, a fellow and director of advanced device architecture at GlobalFoundries. “Improvement in the drive current requires taller fins or high mobility channel materials, such as germanium or III-V.”
Taller fins provide more drive current, enabling faster chips at lower power. But taller fins, and new channel materials, have some drawbacks. “III-V and germanium suffer from a higher off-state leakage, which will increase the standby power. Taller fins also increase device capacitance and hence, active power increases as well on the low backend metal loaded circuits or designs,” Banna said.
With those and other issues in mind, chipmakers may also consider the alternative transistor technology at 7nm—the nanowire FET. The decision largely depends on the strategy, timing and overall readiness for a given company.
“At some point, the finFET is not going to scale anymore,” said An Steegen, senior vice president of process technology at Imec. “And the next thing is likely the lateral nanowire, because it gives more of a window on the electrostatics of your device. You don’t have to scale the width of the nanowire as aggressively as you would have to for the fin.”
Basically, there are two types of nanowire FETs–lateral and vertical. Vertical nanowire FETs are more complex to make in the fab, prompting chipmakers to first look at the lateral version. “Think of (a lateral nanowire FET) as a finFET turned on its side with a gate wrapped all the way around it,” said Michael Chudzik, senior director of strategic planning at Applied Materials. “In vertical FET, it’s a tall wire of silicon. And you wrap a gate around it.”
The lateral nanowire FET, according to Chudzik, is an evolutionary step from the finFET. “Gate-all-around is a pretty attractive option for 7nm or 5nm,” he said. “By 5nm, everyone will be on gate-all-around. Maybe some of the market leaders will be a node ahead of that.”
Nanowire FETs share many of the same process steps as the finFET. Basically, the lateral nanowire FET consists of a substrate. Then, a chipmaker would build super lattice structures on the substrate using silicon or silicon-germanium (SiGe). Then, fins are cut out of the lattice structures. Using today’s fab flow, the gate and source/drain structures are formed on the device. Then, the silicon or SiGe is removed, thereby forming the wires.
The wires run from the source, and through the gate, to the drain, giving it the appearance of a gate-all-around device. The initial nanowire FETs would consist of three stacked wires.
“For 7nm, you could envision the silicon wires themselves being somewhere near 5nm. The space between them is somewhere between 10nm and 12nm,” Chudzik said. “The first introduction would be silicon-based. III-V is a different story. That material set has its own problems that need to be worked out.”
Making lateral nanowire FETs are difficult in mass production, however. The super lattice structures must be precisely developed with good control. “You would also need a process to selectively remove the materials that hold the wires together,” he said. “In gate-all-around, you have channel regions that are non-line-of-sight, meaning they are upside down. You have to conformally put your metal gate and dopants on the underside of these channels.”
And that’s just the tip of the iceberg. And from the device side, GlobalFoundries’ Banna lists five basic challenges and issues for nanowire devices:
1. There is a low drive current per footprint compared to finFETs.
2. There is a penalty when driving long backend metal lines.
3. There is an area penalty in analog/IO circuits when driving large capacitive loads.
4. The access resistance increases due to the reduced contact area.
5. There is a challenge when forming wrapped around gates with good gate dielectric interfaces. Gate resistance and Vth tuning are also challenging.
Another path: Go 3D
Beyond scaling, there is another path. For years, the industry has been talking about the development of 2.5D and 3D chips. So far, though, this segment is taking longer than expected to develop due to a number of challenges.
There is progress, however. Micron has been sampling a stacked-memory, or a 3D DRAM, technology called the Hybrid Memory Cube (HMC). Separately, SK Hynix is ramping up a 3D DRAM technology called High Bandwidth Memory (HBM).
Samsung is developing HBM as well as its own 3D DRAM technology using through-silicon vias (TSVs). “If you take this through-silicon via idea, and you have thousands of through-silicon vias, you can create a very wide data path,” said Mike Williams, vice president of product planning at Samsung. “That allows us to get to bandwidths of up to 512 gigabytes-per-second.”
3D DRAMs, however, are targeted for niche markets. “These are not going into consumer products like cell phones, but more in the high-end server market,” said Prashant Aji, senior technical director at KLA-Tencor.
So when will 2.5D/3D chips move into the mainstream? “It’s not there today,” Aji said. “It’s about two to three years away. People say that cost will be the driver. We feel that functionality will be the driver.”
Still, it’s not going going to happen in a vacuum. “If you think about how to continue Moore’s Law, it’s a simple equation,” said Juan Rey, senior director of engineering for Calibre at Mentor Graphics. “If smaller, lower cost per transistor and better power/performance are not happening, then how do you continue to make it happen? The industry as a whole recognizes there are large volume market areas that still have a need for a Moore’s Law roadmap, even if they don’t get a gain. Large sectors can justify going smaller, more density on a die and lower power. But we also will continue seeing several flavors to this solution.”
Stacked die is just one of those.