Will new materials ever replace CMOS? Probably, but timing is a mystery.
For years, chipmakers have been searching for an alternative material to replace traditional silicon in the channel for advanced CMOS devices at 7nm and beyond. There’s a good reason, too: At 7nm, silicon will likely run out of steam in the channel.
Until recently, chipmakers were counting on III-V materials for the channels, at least for NFET. Compared to silicon, III-V materials provide better mobility, enabling faster devices at low voltages.
But amid a number of challenges, chipmakers have recently pushed out III-V materials at 7nm. Now, III-V is being targeted for 5nm, but many are asking an obvious question—Will III-V ever happen in advanced CMOS?
“That’s a valid question,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “I don’t think anybody can give you a definitive answer right now. A lot of people are working on it. It’s one of those things where I’m not going to do it unless I absolutely have to. And so far, in the 7nm time horizon, it doesn’t look like you absolutely have to. That being said, it could come after that because you may need it.”
Indeed, it’s a mixed picture for III-V. It might be too late to integrate III-V for finFETs at 7nm. But III-V could find a place in a next-generation transistor type at 7nm and beyond, if the industry moves in that direction. “Could it be used in MOSFETs? We are still figuring that out. Could it be the channel materials for a TFET? Those are the kinds of things that could hold promise for III-V,” said Adam Brand, senior director of the transistor technology group at Applied Materials.
In any case, III-V is still in the running at 5nm or sooner, but the industry will require a number of new technologies in the arena. III-V is widely used in RF and optoelectronics, although many of those processes are incompatible with CMOS. As before, III-V semiconductors will require new contact materials, better gate stacks and pristine interfaces.
It also requires new tool technologies, particularly faster epitaxial systems that support 300mm wafers. “The existing (epi) throughputs for III-V are not going to cut it,” said Amy Liu, vice president of U.S. R&D programs at IQE, a supplier of epitaxial wafers for III-V and other applications.
Today, chipmakers are intensifying their focus on the channel, which is a conductive region that connects the source and drain in a device. The big change in the channel transpired at 90nm, when chipmakers introduced strain engineering for PFET. Now, chipmakers are implementing strain techniques for NFET.
But today’s strain technology is under stress. Chipmakers will likely make a materials change in the channels at 10nm or 7nm.
At one time, the leading candidate at 7nm was germanium (Ge) for PFET and a III-V material called indium-gallium-arsenide (InGaAs) for NFET. The industry is dabbling with other III-V compounds for PFET and NFET. Ge has an electron mobility of 3,900cm-square-over-Vs, compared to 1,500cm-square-over-Vs for silicon. InGaAs has an electron mobility of 40,000cm-square-over-Vs.
Ge and III-V are fast but difficult to implement. There is a 4% lattice mismatch between silicon and Ge, and an 8% mismatch between silicon and InGaAs. These mismatches cause dislocations and defects in the materials.
To deal with the lattice mismatch, the device requires buffer and strain relaxation layers between the silicon and III-V materials. The same is true for silicon and Ge. “III-V materials are difficult,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel Corp.. “Changing the channel materials is a big increase in the complexity. You have to worry about how you get this new material on silicon. And you have to worry about making transistors for a very wide span of applications, from high performance to very low leakage. At very low leakage, you are limited by band-to-band tunneling. Sub-threshold leakage may be more of a problem with some III-V materials.”
There are other issues. RF and optoelectronic vendors are equipped to deal with III-V in their fabs, but III-V presents some challenges for CMOS fabs. “Arsenic is so high in III-V. Any out diffusion of arsenic could be a safety hazard and it could cross- contaminate your other wafers,” said Srinivas Banna, a fellow for advanced technology architecture at GlobalFoundries.
So, as a result of the challenges, chipmakers will likely take a simpler approach to the channel at 7nm. They may use silicon for NFET and silicon-germanium for PFET.
III-V isn’t completely out of the picture, however. “In the last year or two, I have detected strong interest on the part of the equipment manufacturers for III-V processes, particularly for InGaAs,” said Jesús del Alamo, a professor in the Department of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (MIT). “So that suggests to me that they are receiving signals from the device manufacturers that they should be ready with processes for contacts, isolation, gate stacks, passivation and more.”
Still, the insertion point for III-V remains a moving target. “The technology is harder and it is taking longer to address the issues. So the current thinking is that perhaps III-V would enter the roadmap maybe at 7nm or perhaps 5nm,” del Alamo said. “What that means is that it would have to be a very advanced 3D design like a finFET. But by then, perhaps even nanowires might be required to make transistors.”
The current school of thought is that the finFET could extend to 7nm. But III-V materials may not be ready, or too difficult to implement, at 7nm.
At 5nm, though, finFETs could hit the wall, prompting the need for a next-generation transistor type. The leading next-generation transistor candidates are gate-all-around FETs, nanowire FETs, quantum-well finFETs, SOI finFETs and tunnel FETs.
All told, it might make more sense to introduce III-V into the channels for a next-generation transistor type at 5nm. But bringing III-V into the CMOS world is no simple task. “The III-Vs have been used for a long time in optical devices, such as lasers and photodiodes, as well as electron devices,” del Alamo said. “The problem is that those technologies are not suitable for a silicon-like manufacturing environment. For III-V, we need new contact technologies, etch techniques and more.”
Assuming that III-V is introduced, chipmakers must first deal with the lattice mismatch issues. To illustrate the complexity, MIT recently described a self-aligned quantum-well MOSFET, which makes use of InGaAs for NFET. The channel consists of InAs, which is sandwiched between two InGaAs layers. It also consists of a 3nm InP barrier layer and an InAlAs buffer layer.
Generally, the III-V layers are grown on a surface using two forms of epitaxy– molecular beam epitaxy (MBE) and metal-organic vapor phase epitaxy (MOVPE). In MBE, the growth of the materials takes place in a high-vacuum environment. MBE is a slow, line-of-sight technique. MOVPE, sometimes called metal-organic chemical vapor deposition (MOCVD), is a process in which reactants are flowed across the substrate.
In Ge channel materials applications, the throughputs for the epi tools are roughly 10 to 15 wafers an hour. For III-V, the epi throughputs are roughly half of those figures, which is too slow for semiconductor production.
Besides the throughput issues, MOCVD is mainly used for 150mm wafer sizes or smaller. But to make III-V happen in CMOS, chipmakers would need to retrofit an MOCVD-like tool, which would have faster throughputs for 300mm wafers. “It would be some sort of a hybrid tool,” IQE’s Liu said.
Then, the next step is to find the right method to integrate III-V on a device. The three contenders are blanket epitaxy, selective epitaxy and wafer bonding. One version of selective epi is called replacement fin.
“One camp says that you put the material down (in a blanket approach) and then etch the III-V with dry etch,” said Bradley Howard, vice president of the Etch Advanced Technology unit at Applied Materials. “I am seeing a lot more interest in the replacement fin. For this, you make your fin in silicon just like we have been doing. And then, you put oxide around the sides of the fin. So you have a mold of oxide around the outside of the sidewalls of the fin. Then you recess the fin down, leaving the oxide mold in place. And then, you come back and put the III-V into that trench where the silicon fin used to be.”
In the wafer bonding approach, a chipmaker patterns III-V materials on top of a donor wafer. That wafer is flipped and the III-V donor wafer is bonded to the main wafer. Then, the donor wafer is removed in an epitaxial lift-off step.
Epi is difficult, but etching is also a challenge. In some cases, traditional wet etch may not work in III-V. It may require new dry etch techniques. “In wet etch, you are only going to deal with wet chemicals. And you are kind of limited by the crystal facets that are in the surface of the materials,” Howard said. “In dry etch, you are not limited by crystal facets or anything like that to get directionality.”
In any case, the industry is making progress in etch. “If you have InGaAs, three atoms need to come out at the right concentration. You must control the etch rates properly, so that one atom doesn’t come out faster. If the surface becomes indium rich, for example, then you have a metal layer with a short circuit. That’s what we can control. So that’s not an issue,” said Reza Arghavani, a fellow at Lam Research.
Another challenge is to find the right contact materials. Contacts are used to connect various parts of the device, such as the source and drain. CMOS devices use silicide-based contacts, which won’t do the trick in III-V.
So, for III-V MOSFETs, the industry is evaluating several contact materials— molybdenum, nickel and others. “We use molybdenum as a contact material. It is silicon compatible, which is very attractive,” MIT’s del Alamo said. “There are a lot of people looking at nickel. However, when you look at the electrical results, nickel is not there.”
In addition, there are other technologies required for III-V chips. The key enabling technology to devise the oxide/semiconductor interface is atomic layer deposition (ALD). CMP and patterning are also critical.
All told, the benefits of III-V in CMOS are too good to pass up, but will it ever happen? “For that to happen, the economics have to work out,” del Alamo said. “That’s one of the challenges.”