When it comes to multi-board and multi-chips-on-a-board designs, do engineers have all the tools they need?
Even though Moore’s Law is running out of steam, there is still a need to increase functional density. Increasingly, this is being done with heterogeneous integration at the package or module level.
This is proving harder than it looks. At this point there are no standardized methodologies, and tools often are retrofitted versions of existing tools that don’t take into account the challenges of multiple-die packages. But as process scaling becomes more difficult and expensive, and as systems become more complex, multi-chip packaging is becoming harder to ignore.
Among the drivers of this trend:
• Higher system performance with lower latency and faster throughput;
• Lower power due to less resistance and shorter distances between components;
• Less congestion with lower system cost, and
• The ability to leverage components such as analog that were developed at older nodes.
Advanced packaging has been gaining momentum in the analog/RF world for the past several years. 2.5D packages have been marketed by companies such as AMD, Huawei, Cisco and IBM for high-speed applications where cost is not a critical element, and they have gotten a giant boost in the past year with the rollout of HBM2 from SK Hynix and Samsung.
Fan-outs have been under development as an alternative to 2.5D. The iPhone 7, introduced in September, is the first mass-market implementation of a fan-out. It is based on TSMC’s Integrated Fan-Out (InFO) process.
As these approaches catch hold, though, questions are surfacing about what else advanced packaging can be used for. And equally important, what is needed to simplify these processes, standardize them to the point where yield is predictable and economies of scale can take effect. That typically leads to a discussion about what can be automated, what tools are needed, and what can be modified to address these issues.
“SerDes doesn’t scale as well as some digital technology, so people are starting to look at operating the SerDes from the actual processor, and integrating that onto some sort of carrier — whether that’s a package or an interposer,” according John Park, product management director for IC packaging and cross-platform solutions at Cadence.
To address this, engineering teams are starting to look for a single environment for the capture of the logic and the sign-off simulation for capturing that system. Historically, there was a connectivity tool for the IC designer, and a separate connectivity tool, and simulation environment for the package and PCB designers.
“Now, however, a lot of people — especially in the analog/RF packaging world — are looking more for a single environment so they can capture their system level schematic as a higher-level schematic than their IC,” Park said. “For example, a design team may take three different ICs and integrate them all together into a single system or system-in-package. Typically, that was done in the past with separate schematics, and people now want to create another level of hierarchy in the schematic capture tool that the chip is already being done in, and use that to drive the system-level implementation. When you do that, there are lots of challenges that come into play. When doing simulation across multiple technologies and even different process nodes, there is all kinds of model conflict. An NPN in one technology/process node is something completely different in the other process nodes, so taking care of how you manage that model collision when you start to integrate all of these different technologies into a single system becomes quite a challenge.”
Along with the demand for this single environment, engineering teams want the ability to include the system-level interconnect, including the layout parasitics, in a single schematic used to drive the implementation. And possibly even more important, they need an LVS sign-off flow. One of the big missing technologies here is layout versus schematic.
“When you have two different design capture environments, that makes it very difficult to perform an LVS check, so this single environment in theory would help simplify that whole process of validating what you have in your IC and system capture environment with what is actually implemented in the system layout environment,” Park added.
At the same time, multiple boards and multiple chips both can sit in the same design thread from initial concept to final product, and they both are the result of high-level partitioning of functions into discrete hardware platforms/fabrics — the product of decisions to engineer portions of a design in-house vs. leveraging COTS ‘components’ (as boards or packaged chips), said Dave Wiens, product marketing manager for the Systems Design Division of Mentor Graphics. “There are multiple ‘packaging’ steps that happen in the design process. Chips are packaged independently, or integrated with other active and passive components inside a mechanical package. Boards are packaged independently, or integrated with other boards inside a mechanical package. In some systems (such as ECUs in an automobile), these packages are integrated with other packages via cable harnesses. And then, of course, there are systems of systems where the integration and packaging can be virtual (in the form of wireless communication) or physical.”
The problem is that today, many of these partitioning decisions are made in isolation from the rest of the design implementation process, and without complete understanding of ICs, packages or boards that could be re-used from previous products, he said. “Tools that intelligently capture the system architecture and integrate the system design stage with functional implementation of multi-board systems and wiring interconnect are now coming on-line. The next generation of design tools will aid in the decision-making and tradeoffs that occur at the functional system partitioning stage with hardware, software, cabling and mechanical enclosures, replacing guesswork with multi-domain virtual prototyping and manual integration steps with automation.”
A compelling option
Multi-chip packaging can be a compelling option if the engineering team can find a way to architect a solution that yields sufficiently, said Mike Gianfagna, vice president of marketing at eSilicon.
eSilicon has been wrestling with this problem for the past several years. The company works with a variety of technologies and provides complex architectural design support that leverages the R&D budgets of its supply chain partners. The company has completed multiple test vehicles — eight in finFET-class designs alone — to come up this learning curve. Among the issues it has encountered are manufacturability, signal and power integrity, thermal integrity and management, warpage and co-planarity specification and analysis, and substrate material definition and development.
On the IP side, there are also challenges — just one of which is to model different latencies. Then, at the architectural level, re-use continues its upward trajectory. Case in point: Marvell’s modular chip concept, MoChi, meant to allow design teams to build a variety of flexible SoCs in modular, LEGO-like format to reduce both time-to-market and cost.
“The difficulty is understanding deadlock, which is prevalent inside chips,” said Anush Mohandass, vice president of marketing and business development at NetSpeed Systems. “If you look at a multi-die architecture, deadlocks become extremely difficult because each of the different dies were designed in isolation, and you don’t know when you put it all together how it’s going to interact. It’s very easy to get into trouble very fast.”
This is where interconnects come into play, and the ability to understand the ramifications of bringing subsystems together; the performance impacts; and formally proving the system is deadlock-free.
While not historically a big concern of chip designers, PCBs play an increasingly important role in advanced packaging. A fan-out is basically a compressed PCB in a package, and a 2.5D package is roughly the same concept using an interposer or some other high-speed interconnect.
Ed Hickey, product engineering director for Allegro PCB editor at Cadence, explained that today, the tools involved in a PCB development flow need to come closer together. “Products are smaller, there is less airflow in them. We need to bring into the PCB world what has been traditionally done in the mechanical world.”
To be sure, the mechanical world is a 3D environment, while the PCB world has been 2D. But where advances have been made in the 3D space, the PCB world needs to figure out collisions to the enclosure and collisions to shields in real time, he said. “The traditional process is to pass back a file from the PCB design tool into the mechanical tool where they can do conflict checking of components to enclosure — where ‘pass files back,’ typically means ‘delay.’ Sometimes the receiver isn’t working that day so you lose a day just trying to get an answer about whether it is okay to put a component in a particular place.”
Another difference between the PCB world of yesteryear and today is that PCB form factors used to be relatively standard: a 15″-by-15″ board. “Today, there are many non-standard PCBs in a range of products, and the process from mechanical to electrical CAD can be very iterative — maybe as many as 30 iterations of design files going back and forth for a variety of reasons. There are so many dynamics in this co-design environment that the MCAD tools and the ECAD tools really need to work in sync because it’s not just mechanical anymore driving the requirements. The PCB designer has a big say in influencing the mechanical requirements. As such, the two teams have to work together in a collaborative way for a product that might be built in the millions,” Hickey continued.
Total system path considerations
While advanced packaging can help soften requirements for timing and signal integrity, rules for both are still an issue. “Certain signals need to be routed to a certain length or delay,” Hickey said. “Traditionally, that’s been a requirement on a board-by-board basis. But today you have to look at the total system path because the propagation of one signal on one board through a connector, perhaps, onto another board — that’s a total system timing path. Usually when trying to meet delay rules, the goal is to match the length of signals across a byte lane, or an interface. To match lengths, typically the trace is elongated, and that takes up real estate on a PCB.”
A common challenge is that one circuit board may be dense, with no place to add this elongation. Then on the mating board, there may be a lot of room there so the designer needs to understand where slack management can happen — and that’s system design.
At the end of the day, rules must be set for a timing path outside of a single board, onto another board, and then determine where best to make a compensation. Unfortunately, this is not a straightforward process today. But as with other issues detailed above, much development work is ongoing in the industry to address, if not solve, these challenges.
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