One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
For years, extreme ultraviolet (EUV) lithography has been a promising technology that was supposed to help enable advanced chip scaling. But after years of R&D, EUV is still not in production despite major backing from the industry, vast resources and billions of dollars in funding.
More recently, though, EUV lithography appears to be inching closer to possible insertion for high-volume manufacturing, at least for one or a few critical layers. Two chipmakers, Intel and Samsung, have put EUV on their roadmaps at 7nm in the 2018 or 2019 timeframe. In addition, Samsung hopes to use EUV for 1xnm DRAMs.
Not everyone is banking on EUV for 7nm, though. TSMC will extend today’s 193nm immersion and multiple patterning to 7nm, with plans to insert EUV at 5nm. GlobalFoundries has a similar strategy. EUV, 193nm immersion and multi-patterning fall under the heading of lithography, which is a key chip-scaling technology that patterns the tiny features on a wafer.
Of course, these roadmaps from chipmakers aren’t set in stone and could easily change, especially if the various pieces of EUV fail to come together at the right time. Right now, EUV is still far from being in production and not a sure thing. Some are still skeptical, saying that EUV has missed the market window and will never happen.
Regardless, chipmakers are all reaching the same consensus—there is a growing urgency for EUV at 7nm and/or 5nm, and perhaps beyond. “At this point, we are really pushing against the wall in terms of not having EUV and relying on only immersion litho,” said Hong Hao, senior vice president of the foundry business at Samsung Semiconductor.
Chipmakers are capable of extending immersion/multi-patterning from 16nm/14nm to 10nm and 7nm. Beyond 7nm, though, there is some uncertainty. Technically, it’s possible to extend conventional lithography using so-called octuple patterning, although this is where it becomes problematic and possibly not worth the trouble.
“Anything is possible,” said Chris Mack, gentlemen scientist and lithography expert. “(The question is whether) it is possible at a cost that makes it worthwhile doing.”
It’s a matter of debate, but chip scaling could slow even further, and perhaps grind to a halt without EUV.
As it turns out, EUV is more difficult to master than previously thought. In fact, it’s arguably the most complex piece of machinery in the history of the IC industry.
In EUV, a power source converts plasma into light at 13.5nm wavelengths. Then the light bounces off several mirrors before hitting the wafer. Today, EUV can print tiny features on a wafer, but the big problem is the power source—it doesn’t generate enough power to enable an EUV scanner go fast enough or make it economically feasible. In fact, there have been several delays with the source, causing EUV to get pushed out from one node to the next.
The tide is slowly turning, however. In fact, the confidence level is gradually increasing for EUV in the industry, according to a recent survey from the eBeam Initiative. Moreover, ASML, the sole supplier of EUV scanners, is making progress with the power source. The EUV resists and masks are also improving. But issues remain involving tool costs, uptime and so-called stochastic phenomena.
All told, EUV is expected to be ready for mass production by 2018 or 2019. If that happens, the industry must get its arms around the technology. But it also must be prepared if EUV stumbles again, which is also possible.
To help the industry get ahead of the curve, Semiconductor Engineering has taken a look at the status of EUV and where chipmakers will use it.
The origins of the technology can be traced back to the 1970s, when the industry was developing X-ray lithography. This technology made use of a giant synchrotron source. But X-ray litho was too expensive and ultimately failed in the 1980s.
Then, X-ray lithography morphed into something called soft X-ray, or EUV. The idea was to develop a more practical reduction system using multi-layer mirrors. The development of EUV started in the 1980s, but the technology began to really gain momentum in the early 2000s. At that time, chipmakers said traditional optical lithography would hit the wall at 65nm or 45nm, prompting the need for a next-generation lithography (NGL) technology.
NGL was supposed to disrupt the landscape. Clearly, those predictions were wrong. NGL is still not ready, and conventional optical lithography has defied the laws of physics and remains the workhorse technology in the fab. Today’s leading-edge, immersion-based lithography scanners use 193nm wavelength light to print tiny features on the wafer.
In reality, though, 193nm lithography reached its limit at 80nm. Still, chipmakers extended 193nm lithography far below this wavelength by using resolution enhancement techniques (RETs).
With RETs, a scanner can print features using a single lithographic exposure at 28nm and above. But starting at 22nm/20nm, single exposure sometimes doesn’t provide enough resolution for the critical layers. Chipmakers solved that problem with multiple patterning, plus a simple two-step process.
“Today, patterning makes use of two fundamental operations,” said Uday Mitra, vice president of etch and patterning strategy at Applied Materials. “The first is line/space. The second is the cuts. The holes also go with the cuts.”
First, a scanner patterns tiny lines on a device. “For line/space, every company is using, and will continue to use SADP and SAQP spacer-based multi-patterning,” Mitra said.
This refers to a technique called self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). SADP/SAQP use one lithography step and additional deposition and etch steps to define a spacer-like feature. Using SADP/SAQP, the pitch extends below 40nm, according to Mitra.
The big challenge is to cut these lines into tiny patterns. For this, chipmakers use double patterning. This process uses two lithography and etch steps to define a single layer. This is called litho-etch-litho-etch (LELE).
Double patterning reduces the pitch by 30%. Triple patterning requires three exposures and etch steps (LELELE). SADP/SAQP can also be used for the cuts.
Regardless, the industry is running into some problems at 10nm and 7nm. At 45nm/40nm, there were 40 mask layers in a design. In comparison, there are 60 mask layers at 14nm and 10nm. “If you push that without EUV, and stretch immersion into triple or quadruple patterning, we expect the mask count to go to about 80 to 85 at 7nm,” said Kelvin Low, senior director of foundry marketing at Samsung.
As the mask count goes up, the cost increases. Overlay is also an issue. Overlay involves the ability of a scanner to align the various mask layers accurately on top of each other. As the mask count increases, overlay becomes a nightmare. If they aren’t aligned, it causes overlay errors.
Plus, it takes 1 to 1.5 days to process a mask layer. With multi-patterning at 7nm, it takes close to five months to ship wafers.
The solution, according to many, is EUV. “With EUV, you replace a bunch of layers,” said Michael Lercel, director of product marketing at ASML. “You’re probably dropping that total (mask) count down into the 60s, if not the 50s. That gets wafers out the door at least a month early.”
EUV is still isn’t ready, however. “For true HVM (high-volume manufacturing), EUV needs to achieve a lot of things simultaneously,” Applied’s Mitra said. “EUV still has a way to go, but the rate of improvement is there. It’s at the state you can do development. But for HVM, where someone is willing to commit thousands of wafers in a manufacturing line, it still has a way to go.”
Not all layers will require EUV. Immersion/multi-patterning will be used for many features.
Unfortunately, though, EUV might be the only option for the critical features in the future. For one thing, the other NGLs are still not ready.
Extending optical with octuple patterning could be problematic. “All of the capabilities are there (for octuple patterning),” Mitra said. “It has its own challenges. How do you manage your distribution? You might have some pitch walking issues. The big challenge is the cuts.”
How it works
Meanwhile, over the years, ASML has shipped several versions of its EUV scanner lines, which are used for R&D. Today, ASML is moving from an 80-watt to a 125-watt source, boosting the throughputs from around 60 wafers an hour (wph) to 85 wph.
Chipmakers want a 250-watt source before they put EUV into production, which equates to 125 wph. Today’s EUV tool availability is 70% to 80%, which is below the industry’s target of 90% or higher.
The big test comes next year when ASML ships its first production-worthy system, the NXE:3400B. It has a numerical aperture of 0.33 and a 13nm resolution. For this, ASML plans to deliver a power source above 200 watts.
The key to all this is the source. Based on a laser-produced-plasma (LPP) technology, the EUV source consists of several parts, including a carbon dioxide (CO²) laser. The laser, which provides power for the source, is located under the fab floor in the sub-fab.
The laser consists of two parts—a seed laser (pre-pulse and main pulse) and a power amplifier. Today’s EUV sources use a 20-kilowatt laser.
The actual EUV source is situated on the fab floor. Attached to the EUV scanner, the source consists of a droplet generator, collector and a vacuum chamber. In EUV, the process takes place in a vacuum environment, because nearly everything absorbs EUV light.
The droplet generator is a small vessel. In operation, tin is loaded into the droplet generator and then heated. At that point, a train of tiny tin droplets flow out from the droplet generator, through a filter and into the vacuum chamber in the source. The droplets are 25 microns in diameter and are falling at a rate of 50,000 times a second.
In the vessel, there is a camera. A droplet passes a certain position in the chamber. Then, the camera tells the seed laser in the sub-fab to fire a laser pulse into the main vacuum chamber. This is called the pre-pulse.
Then comes the really hard part. The pre-pulse laser hits the spherical tin droplet and turns it into a pancake-like shape. Then the laser unit fires again, representing the main pulse. The main pulse hits the pancake-like tin droplet and vaporizes it. “We are trying to hit each droplet twice with the pre-pulse and main-pulse at 50,000 times a second,” ASML’s Lercel said.
At that point, the tin vapor becomes plasma. The plasma, in turn, emits EUV light at 13.5nm wavelengths.
The goal is to hit a droplet with precision. This determines how much of the laser power gets turned into EUV light, which is referred to as conversion efficiency (CE). Today, the CE in ASML’s power source is roughly 5%. “We’ve become better in making the right droplet shape and making the targeting more effective,” Lercel said. “That’s been the huge difference in why we’ve done a lot better in power than in the past.”
Meanwhile, once the EUV light is generated, the photons hit a multi-layer mirror called the collector. The light bounces off the collector and travels through an intermediate focus unit into the scanner.
Over time, though, tin splatters and the material accumulates on the collector. This impacts the CE. So, the collector must be replaced, a time-consuming and expensive process.
To be sure, ASML is addressing these issues. Among the solutions:
• Better droplet generators. The droplet generator can run at 1,400 hours non-stop, a fivefold improvement since last year. The goal is to improve the predictability of the generator.
• Collector cleaning. The collector must be replaced every three months. The goal is to make it a year. Additionally, ASML introduced an in-situ cleaning system for the collector. But the system is still a work in progress.
The collector is just one of the maintenance issues with EUV. EUV is a vacuum-based system. In a vacuum-based system, such as etch and deposition, you must pump the system down. Then, you open up the chamber and fix a potential problem. Pumping down an EUV vacuum chamber is potentially a headache and another source of downtime. “Nobody is talking about that,” said Ben Eynon, a lithography expert. “We need to start talking about things like expected uptime and cost-of-ownership for consumables such as the collector.”
• 250 Watt source. ASML and Gigaphoton are working on this, but the industry needs a 250 Watt source to get EUV into production by 2018/2019.
• Pellicle An EUV pellicle is a requirement. ASML and others are making progress in the arena.
Scanning the wafer
Meanwhile, EUV light is propelled into the scanner. In the scanner, the light bounces off a complex scheme of 10 surfaces or multi-layer mirrors. First, the light goes through a programmable illuminator. This forms a pupil shape to illuminate the right amount of light for the EUV mask.
Then, EUV light hits the mask, which is also reflective. It bounces off six multi-layer mirrors in the projection optics. Finally, the light hits the wafer at an angle of 6%.
Each multi-layer mirror reflects about 70% of the light. Based on various calculations, the EUV scanner itself has a transmission rate of only 4%.
Meanwhile, following those events, the wafer is then processed. First, the light hits the photoresist on the wafer. Resists are light-sensitive materials. They form patterns on a surface when exposed to light.
Today, EUV resists have sensitivities around 31 millijoules per cm², which is below the desired targets. “If we have resist sensitivities of 20 millijoules per centimeter square, we can get close to cost parity with immersion triple patterning,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.
With 30mJ/cm2 resists, an EUV scanner with a 125-watt source produces 70 wph, analyst said. But at 75% to 80% uptimes, the actual utilization for EUV in the fab is 50%, or 840 wafers per day, analysts said.
With the same resists, an EUV scanner with a 250-watt source produces 90 wph. At 90% uptimes, the utilization for EUV is only 70%, analysts said.
EUV resists have other issues. “In EUV, you suffer from yield because of a stochastic phenomenon, line-edge roughness and contact-hole roughness caused by photon shot noise and other sources,” according to lithography expert Mack.
Line-edge roughness (LER) is problematic in EUV. “LER is a linewidth variation,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “It doesn’t scale with the feature size.”
There are other issues. “If a lot of those issues are resolved, you can use EUV for the cuts and holes. What EUV still doesn’t address is edge placement error (EPE),” Applied’s Mitra said. EPE is measured as the difference between the intended and printed features in a layout.
EUV in the field
Fortunately, though, chipmakers can use today’s immersion/multi-patterning at 16nm/14nm and 10nm.
It’s a different story at 7nm. Samsung, for one, is pushing EUV for 7nm. “7nm, without EUV, will be a costly node in terms of not only fabrication, wafer costs and mask costs, but also design costs and development times,” Samsung’s Hao said.
TSMC, however, plans to extend immersion/multi-patterning to 7nm for time-to-market reasons. TSMC hopes to beat its rivals to 7nm, so EUV won’t be ready in time for the company.
This leaves foundry customers with some tough choices. “If you decide to do 193nm/multi-patterning for 7nm, that puts a huge set of constraints on your chip design. It changes the way you do design,” lithography expert Mack said. “If you use EUV, you end up with a different design strategy at some of the critical levels. You need to know that at least two years, or maybe three years, ahead of manufacturing. That’s how long it takes to lay out a chip.”
But if EUV happens, where will chipmakers use it? First, it must make economic sense. “Introduction and production at this point is a question of when and not if. EUV lithography is highly desirable for the 7nm node, but we’ll only use it when it’s ready,” said Mark Phillips, a fellow and director of lithography hardware and solutions at Intel, at the SPIE Advanced Lithography event earlier this year. “We must use EUV carefully. We need to replace at least three 193nm masks, plus other process steps in the flow for multiple patterning, in order for it to be cost effective.”
Others agree. “There is a real possibility we will see EUV at one or some levels in 7nm,” said David Fried, chief technology officer at Coventor. “When EUV is introduced, it will likely be at some very tight cuts, such as fin-block, gate-cut or Mx-cut. It will likely be used for holes, such as contacts or vias.”
EUV won’t be used everywhere. “The tightest quasi-1D levels, such as the fin, gate and Mx, will still likely use immersion/multi-patterning,” Fried said.
Still, there is some confusion. EUV is a 13.5nm technology. Yet chipmakers are talking about 7nm chips. So, will EUV need to pattern 7nm chips below 13.5nm? Will it require double patterning?
Simply put, 7nm is a marketing term. It doesn’t really have 7nm line/spaces. “EUV will be able to pattern some, if not most, layers at 7nm/5nm using single exposure,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics.
The decision on which layers will use what techniques boils down to cost. “For some layers, DUV with multi-patterning will be cheaper than EUV,” Abercrombie said. “For some layers, EUV may require multi-patterning to work at all. I fear that there may be some marketing pressure to push layers to EUV that could be done more cheaply with DUV multi-patterning just to be able to say that ‘this technology node requires no multi-patterning’ or ‘we use fewer masks than the other guys.’ Using fewer masks does not necessarily mean less cost.”
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