Investments in finFET technology are hard to discard, but technical and financial challenges for getting there are huge.
Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017.
So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few companies will be able to afford it, and the chips may appear in just a narrow set of applications.
Still, the industry is aggressively working on 5nm in R&D, although it’s unclear if the technology will appear on schedule by the 2020 timeframe. Even today, foundries are struggling to keep pace with the traditional two-year process cadence, raising questions about the future of chip scaling and Moore’s Law.
Indeed, citing the cost and complexity of the technology, Bob Johnson, an analyst at Gartner, projects that 7nm could get pushed out to 2020. This is roughly a year or two later than expected based on some chipmakers’ roadmaps.
This, in turn, could impact the potential timing of 5nm, if the industry decides to move forward with the technology. “I assume 5nm will happen, but not by 2020,” Johnson said, adding that a viable 5nm process may not appear until the next decade, possibly 2023.
But assuming that 5nm happens at one time or another, chipmakers are currently re-evaluating the transistor options at 5nm, and in the process, they are revising the industry roadmap. Under the previous roadmap, the finFET was supposed to extend to 7nm and then run out of gas. Then, the industry would need a new transistor type at 5nm. At one time, the sole contender for 5nm was the lateral nanowire FET, sometimes called the gate-all-around FET.
The lateral nanowire FET is a finFET turned on its side with a gate wrapped around it. Nanowire FETs have good electrostatics, but they are also difficult and expensive to make, prompting the industry to reconsider the transistor options.
Now, there are two main transistor contenders at 5nm. The nanowire FET remains one candidate, but the industry now believes it can extend the finFET to 5nm. “FinFETs could be extended to 5nm,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “FinFETS are not the only option for 5nm.”
To enable 5nm, though, the industry will require new breakthroughs in the fab. Lithography is the obvious challenge. But another technology, the interconnect, is becoming the biggest roadblock. “That’s the grand challenge,” said Mark Rodder, senior vice president of the Advanced Logic Lab at Samsung. “We really need a breakthrough in the interconnect.”
With those and other challenges in mind, the industry is reaching the same conclusion. “5nm is an expensive node,” said Aaron Thean, vice president of process technologies and director of the logic devices R&D program at IMEC.
These and other factors are prompting chipmakers to consider a parallel path. For example, advanced stacked die, monolithic 3D and other 2.5D/3D IC technologies could also play a role at future nodes.
What is 5nm?
In any case, the questions are clear about 5nm. Will 5nm ever happen? And what are the future applications?
And for that matter, what does the designation “5nm” mean in the first place? Right now, it’s a mystery.
Even today, the nomenclatures and definitions of the process nodes are fuzzy, if not confusing. For example, foundry vendors have slightly different specs at 16nm/14nm. The same scenario will likely happen at 10nm and 7nm.
By 5nm, the node designations may become irrelevant. Right now, though, the industry is aiming to develop what it calls a “true 5nm” technology.
For this, chipmakers hope to follow the traditional transistor scaling metrics, as dictated by Moore’s Law. The idea is to scale or multiply the key transistor specs by 0.7x and/or 0.8x at each node, which, in turn, will roughly double the transistor density.
One way to determine the 5nm specs is to take Intel’s 14nm technology and multiply that by 0.7x or 0.8x. Intel’s 14nm technology has a 20nm gate length, analysts said. By using the 0.8x metric, a 5nm transistor would have a 10nm to 12nm gate length, analysts said.
The specs are just part of the equation. As before, a chip must provide good performance at low power. “Typically, we look for at least a 20% performance improvement at the same power (at each node), or a 40% power reduction at the same frequency,” said Srinivasa Banna, a fellow and director of advanced device architecture at GlobalFoundries.
If 5nm can meet these criteria, the technology could find a place in several future markets. “We will come up new features for the mobile market as well as the high-end data center,” Banna said.
A future transistor can meet the given specs. But more importantly, it must be production worthy. “Performance and cost concerns are the big challenges in scaling to 5nm, and addressing them will involve extension of current approaches as well as the introduction of new technologies and materials,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research.
Patterning is one the challenges at 5nm. For this, the industry wants extreme ultraviolet (EUV) lithography. But if EUV misses the window, chipmakers may attempt to extend 193nm immersion. “A 5nm process with EUV should be cheaper than a 5nm process without it, but either version may be so expensive that increasingly fewer companies could afford it,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics.
On this front, the question is clear–Will EUV ever happen? The mood is changing for EUV. In a recent survey, conducted by the eBeam Initiative, respondents predicted that EUV will be used in at least one manufacturing step by 2020, with an average confidence rating of 62%.
All told, the success or failure of 5nm may boil down to one factor—cost “There has to be some value,” said Bruce Doris, a researcher at IBM. “It definitely must have some cost advantages, or there is not much point to do it.”
Meanwhile, if 5nm happens, here’s the next question: What’s the best transistor option for 5nm? It’s still up in the air. “We are looking at a lot of options,” Samsung’s Rodder said. “There are many options and issues.”
Surprisingly, though, the nanowire FET, or gate-all-around FET, is no longer the lone candidate. Now, there are a growing number of technologists that want to extend the finFET to 5nm.
IBM’s Doris, for one, contends that the finFET transistor would be a better option at 5nm, as opposed to the nanowire FET. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
Some want to extend the finFET, and for good reason. The industry has poured billions of dollars into the development of finFET technology, including EDA tools, processes and fab gear. So to get a return-on-investment, some want to milk the finFET as long as possible.
“If I’m in charge of the technology landscape for 5nm, I am going to tell the engineers, ‘Look, we have finFETs for 14nm, 10nm and maybe 7nm,'” Doris said. “So I would twist everybody’s arm to see if we can get another generation out of that. My demand is to have a 5nm finFET.”
Scaling the finFET to 5nm is a difficult task, however. For example, a hypothetical 7nm finFET is projected to have a 12nm to 18nm gate length and a 45nm to 55nm gate pitch, according to IBM. It could have a fin width of 6nm and a contacted poly pitch (CPP) of 44nm.
In comparison, a hypothetical 5nm finFET could have a 9nm gate length, a 35nm gate pitch and a 30nm CPP, according to IBM. It would also have a fin width of 5nm, which, in theory, is the physical limit of this particular structure.
To extend the finFET, chipmakers would require several innovations, such as taller fins and new channel materials. Taller fins provide more drive current, enabling faster chips at lower power.
But like the fin width, the fin height also has some limitations. “There is an optimum point for the height of the fin,” GlobalFoundries’ Banna said. “Beyond that you don’t get the benefits of increasing the fin height.”
New channel materials, such as III-V and germanium (Ge), promise to boost the channel mobility in devices. “III-V and germanium suffer from a higher off-state leakage, which will increase the standby power,” Banna said.
For this reason and others, chipmakers are also looking at the alternative transistor candidate at 5nm—the lateral nanowire FET or gate-all-around. Nanowire FETs, an evolutionary step from the finFET, appears to be a viable technology.
In a recent paper given at IEDM, for example, Intel described a nanowire FET with a gate length of 13nm and a device width of 4.7nm. In addition, Intel benchmarked various channel materials for the device, concluding that III-V and Ge each have their individual merits.
“Our study indicates that when optimizing for the best drive current and energy versus delay, nanowires should use Ge NMOS and Ge PMOS,” said Raseong Kim, a senior process engineer at Intel. “When optimizing for the lowest capacitance and power, nanowires should use III-V NMOS and Ge PMOS.”
All told, the nanowire FET has some advantages. “Gate-all-around is the way to go at 5nm,” said Michael Chudzik, senior director of strategic planning at Applied Materials. “It increases the gate area, so that you are more effective at turning off the device.”
There are some challenges, however. “Capacitance is the number one problem with gate-all-around. Unlike finFETs, you have added capacitance between the gate and the source-drain, because of the nanowire architecture,” Chudzik said. “Plus, you’re building the nanowires on a silicon surface. You need to shut that off, because that’s a parasitic transistor. And that capacitance is more important in gate-all-around than it is in a finFET.”
Scaling the transistor isn’t the only option, however. In fact, another path is to go vertical. One option is to go the 2.5D stacked-die route, which is gaining steam. Another option is to use a 3D scheme.
If it’s based on cost alone, 2.5D/3D staked-die reach a cost-per-transistor parity with traditional chips at 7nm, analysts said. By 5nm, 2.5D/3D could have a 15% to 20% cost advantage, they added.
For 2.5D/3D stacked-die, cost isn’t the only factor. “People say that cost will be the driver,” said Prashant Aji, senior technical director at KLA-Tencor. “We feel that functionality will be the driver.”
Other options are also on the table. For example, advanced chips can be integrated into other 2.5D-like packages, such as fan-out. Then, there is Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology, which is a low-cost alternative to an interposer. “As Moore’s Law is slowing down, people are using the buzzwords ‘More than Moore’ and IoT. A lot of those are enabled by packaging,” KLA-Tencor’s Aji said.