Atomic Layer Etch Heats Up

The atomic layer etch (ALE) market is starting to heat up as chipmakers push to 10nm and beyond.

ALE is a promising next-generation etch technology that has been in R&D for the last several years, but until now there has been little or no need to use it. Unlike conventional etch tools, which remove materials on a continuous basis, ALE promises to selectively and precisely remove targeted materials at the atomic scale.

It now is moving from the lab to the fab. Applied Materials, for example, has officially entered the next-generation etch market by rolling out a new tool technology. Applied describes its technology as an “extreme selectivity” etch tool, although the system basically falls in the generic category of ALE.

Meanwhile, Hitachi High-Technologies, LAM Research and Tokyo Electron Ltd. (TEL) are also working on ALE tools.

If it lives up to its promises, this technology could help enable the next wave of scaled memory and logic devices. For example, in a 16nm/14nm finFET, the trenches or gaps between the individual fins might be on the order of about 40 angstroms or roughly 10 atoms across. (An angstrom is 0.1nm.) As the industry migrates from 10nm to 7nm finFETs, the trenches or gaps between the fins will shrink to between 10 to 15 angstroms or 5 atoms across.

Typically, chipmakers use an etch tool to remove materials within these tiny trenches during the fabrication flow. But there are signs that conventional etch tools are struggling to do this job at these advanced nodes. So to perform this difficult task, the industry may require a new class of etch tools like ALE that can selectively remove ultra-thin materials or mere atoms without damaging the structure around it.

“People are asking us for this level of capability,” said Shankar Venkataraman, general manager of the Selective Removal Products division at Applied Materials. “When you talk about atomic level, you are talking about a very fine level of etching. The gaps might be 10 or 15 angstroms. You have to remove material from within those gaps with selectively around it.”

ALE is just one of the technologies required for chip scaling. In fact, the industry will require a host of innovative techniques that can process structures at the atomic level.

“We need to take a different approach,” said Rick Gottscho, executive vice president of global products at Lam Research, during a keynote address at the recent SPIE Advanced Lithography conference. “That approach is atomic layer processing.”

Atomic layer processing involves ALE and a related technology, atomic layer deposition (ALD). Generally, ALD is a process that deposits materials layer-by-layer at the atomic level, enabling thin and conformal films on devices. While ALE is just moving into the fab, ALD has been in production for several years. ALD is used in several applications, such as high-k/metal gate and multiple patterning.

Going forward, chipmakers will use both ALD and ALE in select applications, although there are some tradeoffs. Both ALD and ALE are slower and more expensive than conventional tools. And for that reason and others, chipmakers will continue to use conventional deposition and etch tools for workhorse applications in the fab.

What is ALE?
Etch, the art of removing materials in a structure, is a critical step in the fab. It is used for the production of most, if not all, device types, such as analog, logic, memory and MEMS.

Generally, etch is growing faster than the overall equipment market, due to the surge in multiple patterning for memory and logic. Deposition and etch are the key steps in multi-patterning.

In total, the etch equipment market reached $6.2 billion in 2015, up 11% from 2014, according to Takashi Ogawa, an analyst with Gartner. The overall wafer fab equipment (WFE) market fell by 1.3% in 2015, according to Gartner.

“In our Q1 forecast, we think the etch market will have positive growth to $6.221 billion in 2016, while the total WFE market will be negative 1.8%,” Ogawa said.

Meanwhile, etch can be divided into two categories—wet and dry. Wet etch uses liquid chemicals to remove materials. Dry etch, the bigger of the two markets, bombards ions on a surface as a means to remove materials.

For decades, chipmakers have used a dry etch technology, called reactive ion etch (RIE), in the fab. RIE is a continuous technology, meaning the reactions take place throughout the process.

RIE tools are fast and reliable, but there are some issues. “In the early days, we just had one power source and a few gases,” Lam’s Gottscho said. “Now we have 20 something gases and multiple power sources.”

The chemistries also involve a complex mixture of ions and neutrals. “It’s a soup that’s difficult to control,” Gottscho said.

There are other issues. “In a traditional directional etcher, what you will have is plasma directly above the wafer and actually bombarding the wafer with ions,” said Matt Cogorno, global product manager at Applied Materials. “We don’t want to do that because that can cause damage to the wafer. So for some of these applications, where you want very gentle chemical etch, we only want radical species to come through.”

All told, RIE, as well as wet etch, will continue to be used in the fab. But they are being stretched to the limits, at least for some of the more difficult applications in memory and logic.

To solve those problems, the industry has been developing ALE. But ALE has been stuck in R&D for several years due to challenges with throughput and other issues. Now, ALE is finally ready for prime time.

But what exactly is ALE and selective removal? “ALE is mono-layer etching with etch-cycle dynamics from etchant adsorption to etching product desorption,” Gartner’s Ogawa said. “Meanwhile, selective removal in general is etching for selected materials or spaces by masking.”

In either case, the technology is trying to achieve the same goal. “You deposit a variety of materials and then selectively remove what you don’t want,” Applied’s Cogorno said. “[It’s] the ability to remove one material selectively to all of the others that are exposed on the wafer.”

Not all ALE tools are the same, however. Tool vendors that are fielding or developing ALE appear to be taking different approaches.

For some time, Lam Research has been talking about ALE. Basically, the company is implementing more of a traditional and sequential ALE process. For this, the desired chemistry is first pumped into a chamber and dispersed on the surface. This step, called “reaction A,” forms a reactive layer on the surface. Then, there is a removal step, called “reaction B.” In this step, ions or other chemistries remove the undesired parts of the structure. The steps are then repeated.

Generally, chlorine is one of the more common reactants (reaction A) used for silicon, germanium and III-V materials, according to Lam Research. Argon can be used for the removal step. In total, the industry has evaluated some 20 materials for ALE, according to Lam.

There are other approaches as well. For example, Applied Materials has rolled out the Producer Selectra system. “In our chamber, there are two areas. The top area is where we create the etching chemistry. We use plasma to generate this etching chemistry. It’s a mixture of ions, radicals and neutrals,” Applied’s Cogorno said.

The system also includes hardware that blocks the undesired ions, allowing the desired chemistry to disperse on the surface. What’s more, it’s a non-line-of-sight technology. “That is how we can generate damage-free chemical etch with extreme selectively,” Cogorno said.

Meanwhile, Hitachi High-Technologies has two ALE offerings. “One utilizes our ECR technology with several hardware modifications for high-throughput capability,” said Yohei Ishii, senior process engineer at Hitachi High-Technologies America. “The other chamber provides reverse ALD process capability without surface damage to the non-etched layers.”

ALE is geared for both logic and memory. “As long as high selectivity and low damage are needed, ALE can be one of the candidates,” Ishii said. “However, at this point, our targeted market is logic-based processing. In sub-10nm logic technology nodes, some of the etching processes require very high selectivity/low damage.

“ALE is a technology enabler and targeted at a limited number of layers currently. Some of the critical dry etch processes that needs extremely high selectivity, and minimal damage, may be replaced by ALE processes. Due to the slow process throughput currently, some processes may not be replaced. Not all processes need atomic level control of etching,” Ishii said.

The benefits of ALE and selective removal are obvious, but the industry faces some challenges with both the new and traditional etch techniques at advanced nodes.

“It all comes down to variation,” said David Fried, chief technology officer at Coventor. “The tolerances on these processes for 7nm and beyond are getting to the atomic scale, if they’re not there already. A significant driver of these intense process tolerances are the multi-patterning schemes being used to hold the industry together while waiting for EUV.

“Conventional deposition and etch processes have been tuned for variation to an amazing level. And it’s not the nominal process target that’s challenging,” Fried said. “It’s the fact that if an etcher knocks off a single extra silicon atom, you have just introduced a local half-nm variation.”

With those issues in mind, both deposition and etch will need to work in tandem at advanced nodes. “This means these processes will need to be engineered to either deposit or remove single layers of atoms at a time,” he said.

But atomic level processes, including ALD and ALE, will be used for some but not all layers. “It’s going to be very difficult to make these processes cost effective, as compared to conventional deposition and etch,” he said. “So, the insertion of these (atomic-level) processes will need to be really surgical. Engineers will need to be very smart to prioritize the deposition and etch applications, where the variation reduction is worth the extra process time and cost.”

The ALE apps
So, the next question is clear: Where would chipmakers use ALE and selective removal?

In fact, there is a growing list of potential applications. “As devices have scaled, it is very difficult to remove interfacial oxide layers in smaller contacts using conventional dry etching,” said Han Jin Lim, a technical member at Samsung Semiconductor’s R&D Center. “By using ALE, we expect the removal of interfacial oxide layers like native oxide effectively.”

ALE is ideal for other applications. “In other cases, silicon damage near the transistor will be reduced by ALE,” Lim said.

What’s more, ALE could be used in some of the more difficult steps in the finFET flow. As stated above, the ability to remove materials in tiny trenches in finFETs is just one application.

Another application is multiple patterning. One of the first steps in the finFET flow is to pattern the device using self-aligned double or quadruple patterning.

In the flow, the spacer-based structures must be uniform. “Extreme selectively is needed for this nitride spacer,” Applied’s Cogorno said. “In order to make this work, you need to remove this silicon completely without any residues at the bottom or it will mess up your pattern.”

Fin trimming, meanwhile, is another application. For example, in Intel’s first-generation finFETs at 22nm, the fins were relatively short and tapered. Then, at 14nm, Intel went to taller and thinner fins. The fins are also more rectangular in shape. Taller and rectangular fins enable more drive current in the device.

Other chipmakers are moving in the same direction. The shapes and sizes of the fins must be precise. If they aren’t precise, the fins must be trimmed in the fab flow.

The ability to trim these structures becomes more difficult at 10nm and beyond. “With scaled fins, they need to get thinner and taller. You need to finely trim it. How do you finely trim it without bombarding it and having plasma damage?” Applied’s Venkataraman said. “With [selective removal] we are able to remove as little as 6 angstroms of materials during our process, which is just a little bit more than just 2 atoms of silicon.”

Besides finFETs, ALE will be one of the keys to enable the next-generation transistor—the nanowire FET or gate-all-around FET. In addition, ALE can also be used for 3D NAND and DRAM.

Time will tell if ALE will live up to its promises. But chipmakers may have little or no choice to make it work, especially as they continue to process chips at the atomic level.

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