category: Manufacturing, Packaging and Materials

category: Auto, Security & Edge AI

CMOS Area Scaling And The Need For High Aspect Ratio Vias
By Coventor - 26 Oct, 2018 - Comments: 0

Resolving internal routing congestion will be essential to enable CMOS area scaling to the N5 node and beyond. The solution will require new design maneuvers in place and route (PnR), as well as patterning innovations. In this work, we present inter-layer high aspect ratio vias or ‘SuperVia’ (SV) as one technology element that could enable track height scaling to 4.5T at aggressive N5 dime... » read more

In-Cell Overlay Metrology By Using Optical Metrology Tool
By KLA - 26 Oct, 2018 - Comments: 0

By Honggoo Lee, Sangjun Han, Minhyung Hong, Seungyong Kima, Jieun Lee, DongYoung Leea, Eungryong Oh, and Ahlin Choi of SK Hynix, and Hyowon Park, Waley Liang, DongSub Choi, Nakyoon Kim, Jeongpyo Lee, Stilian Pandev, Sanghuck Jeon, John C. Robinson of KLA-Tencor Abstract Overlay is one of the most critical process control steps of semiconductor manufacturing technology. A typical advanced s... » read more

3D NAND: Challenges Beyond 96-Layer Memory Arrays
By Steve Shih-Wei Wang - 24 Oct, 2018 - Comments: 0

Unlike scaling practices in 2D NAND technology, the direct way to reduce bit costs and increase chip density in 3D NAND is by adding layers. In 2013, Samsung shipped the first V-NAND product using 24 layers and MLC [1]. Five years later, in 2018, vendors of 3D-NAND have all announced production plans for 96-Layer NAND using TLC [2]. According to recent news reports, vendors are already working ... » read more

Manufacturing Bits: Oct. 23
By Mark LaPedus - 23 Oct, 2018 - Comments: 0

3D stacked finFETs At the upcoming 2018 IEEE International Electron Devices Meeting (IEDM), Imec is expected to present a paper on a 3D stacked finFET architecture. IEDM is slated from Dec. 1-5 in San Francisco. Imec’s technology is based what on the R&D organization calls sequential integration. Another R&D organization, Leti, calls it 3D monolithic integration. Regardless, the idea... » read more

A Crisis In DoD’s Trusted Foundry Program?
By Mark LaPedus - 22 Oct, 2018 - Comments: 0

The U.S. Department of Defense’s Trusted Foundry program is in flux due to GlobalFoundries’ recent decision to put 7nm on hold, raising national security concerns across the U.S. defense community. U.S. DoD and military/aerospace chip customers currently have access to U.S.-based “secure” foundry capacity down to 14nm, but that's where it ends. No other foundries provide similar “s... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Oct, 2018 - Comments: 0

Chipmakers Amid ongoing delays with its 10nm process, Intel has reorganized its manufacturing unit, according to a report from The Oregonian/OregonLive. Sohail Ahmed, who has jointly led the unit since 2016, will retire next month, according to the report. The industry is racing to put extreme ultraviolet (EUV) lithography into production. TSMC recently taped-out its first 7nm chip using E... » read more

EUV’s Uncertain Future
By Ed Sperling - 18 Oct, 2018 - Comments: 8

The ground appears to be solidifying under EUV. Intel announced this week it is reducing its stake in ASML to less than 3%, the second such move in a year. Apparently ASML no longer needs outside help. According to the company's earnings report, ASML turned in net sales of €2.776 billion, a slight increase over the €2.447 billion (GAAP) the company reported in Q3 and way up over the €... » read more

Silicon Wafers: Tight Supply, High Prices
By Mark LaPedus - 18 Oct, 2018 - Comments: 0

For years, the silicon wafer industry suffered from oversupply and depressed prices, causing considerable consolidation in the industry. Then, two or so years ago, the IC industry entered into a boom cycle. Silicon wafer vendors began to experience tight supply amid strong demand from IC makers. Some silicon wafer makers even raised their prices. Today, the silicon wafer market remains st... » read more

Digging Deep Into High Aspect Ratio Process Control For Memory Technology
By Mark Shirey - 18 Oct, 2018 - Comments: 0

By Mark Shirey and Janay Camp Data is an integral part of our lives. Contrary to the past, where files had to be removed periodically to free up storage space, we now assume that our data will never be deleted. Why risk deleting the wrong file? Just keep them! This new approach consumes a lot of memory, and intensifies the demand for storage. Two of the main workhorses of the memory segment ... » read more

Wanted: Mask Equipment for Mature Nodes
By Mark LaPedus - 18 Oct, 2018 - Comments: 0

Rising demand for chips at mature nodes is impacting the photomask supply chain, causing huge demand for trailing-edge masks and a shortfall of older mask equipment. The big issue is the equipment shortfall, which could impact customers on several fronts. Tool shortages could lead to longer mask turnaround times and delivery schedules for chips being developed at 90nm and above, which are bu... » read more

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