The Race To Zero Defects


By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science


Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

Cobalt Shortages Ahead


Rapid growth of electric vehicles is creating an enormous demand for cobalt, causing tight supply, high prices and supply chain issues for this critical material. Cobalt is a ferromagnetic metal and one of the key materials used in lithium-ion batteries for cell phones, notebook PCs, battery-electric cars and hybrids. It also is used in alloys and semiconductors. And while the IC industry co... » read more

Digital Fabrication’s Promise And Potential Pitfalls


Semiconductor functionality continues to expand, enabling robotic machines to analyze problems, make decisions and communicate information better than ever. These capabilities open the door for new applications such as Industry 4.0, a term now commonly used throughout Europe and the U.S. (more on Japan’s interpretation to follow). By integrating the performance capabilities of the Internet of... » read more

Tessent Cell-Aware Test


Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

Old Vs. New Packages


Over the years, the semiconductor industry has witnessed a parade of packaging innovations, such as system-in-package, semiconductor embedded in substrate, and fan-out wafer-level packaging. Two interesting packaging innovations are now being used in the process of miniaturizing microchips and electronics. One is a new concept that combines two tried-and-true technologies. The other is a de... » read more

Who’s Paying For Auto Chip Test?


Testing of automotive chips is becoming more difficult and time-consuming, and the problem is only going to get worse. There is more to this than simply developing new test equipment or devising a better design for test flow. There are multiple issues at play here, and some of them are at odds with the others. First, no one has experience using advanced-node chips in extreme environments.... » read more

The Chiplet Race Begins


Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

Chord Signaling by Generalizing Differential Signals


Chord signaling is a multi-wire signaling approach that is a generalization of differential signaling. With differential signaling, a single bit is transmitted on two correlated wires. In Chord signaling, n bits are transmitted on n+1 correlated wires. The number of wires, the Chordal code and the design of the multi-input comparators together. Background Companies connect chips in elect... » read more

Return Of The Organic Interposer


Organic interposers are resurfacing as an option in advanced packaging, several years after they were first proposed as a means of reducing costs in 2.5D multi-die configurations. There are several reasons why there is a renewed interest in this technology: More companies are pushing up against the limits of Moore's Law, where the cost of continuing to shrinking features is exorbitant. ... » read more

← Older posts Newer posts →