category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Customer-Developed, Hyper-Convergent Design Flows Are Now Possible
By John Faase - 25 Jan, 2021 - Comments: 0

We all know the days of sequential, compartmentalized chip design are over. In advanced technology nodes, placement impacts performance, performance impacts power, and routing impacts everything. The way to manage these challenges is to interleave design tasks. For example, provide information on late-stage routing to early-stage synthesis tools to improve convergence. This technique is commonl... » read more

Too Much Fab And Test Data, Low Utilization
By Anne Meixner - 12 Jan, 2021 - Comments: 7

Can there be such a thing as too much data in the semiconductor and electronics manufacturing process? The answer is, it depends. An estimated 80% or more of the data collected across the semiconductor supply chain is never looked at, from design to manufacturing and out into the field. While this may be surprising, there are some good reasons: Engineers only look at data necessary to s... » read more

Testing Silicon Photonics In Production
By Bryon Moyer - 12 Jan, 2021 - Comments: 1

As silicon photonics costs come down, the technology is being worked into new applications, from connectivity to AI. But full commercial production requires testing those photonic circuits before shipping them. Photonics testing is only getting started. Volume production is still not happening, and test equipment and techniques are still being developed. What exists today is a blend of exist... » read more

DFT For SoCs Is Last, First, And Everywhere In Between
By Robert Ruiz - 12 Jan, 2021 - Comments: 0

Back in the dawn of time, IC test was the last task in the design flow. First, you designed the chip and then you wrote the functional test program to verify it performed as expected after manufacturing. Without much effort, some portion of the functional test program was often reused as the manufacturing test to determine that the silicon was defect-free. Fast forward to today and things ha... » read more

Using Analytics To Reduce Burn-in
By Anne Meixner - 12 Jan, 2021 - Comments: 3

Silicon providers are using adaptive test flows to reduce burn-in costs, one of the many approaches aimed at stemming cost increases at advanced nodes and in advanced packages. No one likes it when their cell phone fails within the first month of ownership. But the problems are much more pressing when the key components in data warehouse servers or automobiles fail. Reliability expectations ... » read more

System-Level Test Methodologies Take Center Stage
By Fabio Pizza - 12 Jan, 2021 - Comments: 0

Because electronic systems for all applications in end-user markets must provide the highest possible reliability to match customers’ quality expectations, semiconductor components undergo multiple tests and stress steps to screen out defects that could arise during their lifecycle. Due to new semiconductor devices’ increasing design complexity and extreme process technology, increased test... » read more

Part Average Test (PAT)
By yieldHUB - 12 Jan, 2021 - Comments: 0

With semiconductor manufacturers producing huge amounts of data, it can be hard to guarantee quality and reliability, even with internal tools. Many companies outsource Part Average Testing (PAT) to a bespoke yield management provider. Provided they meet the standards set out by AEC, the tool will be invaluable in guaranteeing quality and reliability for your customers. Click here to con... » read more

Photonic Integration Based On A Ferroelectric Thin-Film Platform
By Advantest - 11 Jan, 2021 - Comments: 0

Photonic-integrated circuits (PICs) using ferroelectric materials are expected to be used in many applications because of its unique optical properties such as large electrooptic coefficients. In this study, a novel PIC based on a ferroelectric thin-film platform was designed and fabricated, where high-speed optical modulator, spot-size converters (SSCs), and a variable optical attenuator (VOA)... » read more

Multi-Layer Deep Data Performance Monitoring And Optimization
By proteanTecs - 11 Jan, 2021 - Comments: 0

Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementa... » read more

Full Metrology Solutions For Advanced RF With Picosecond Ultrasonic Metrology
By Onto Innovation - 11 Jan, 2021 - Comments: 0

Picosecond Ultrasonics (PULSE Technology) has been widely used in thin metal film metrology because of its unique advantages, such as being a rapid, non-contact, non-destructive technology and its capabilities for simultaneous multiple layer measurement. Measuring velocity and thickness simultaneously for transparent and semi-transparent films offers a lot of potential for not only monitoring ... » read more

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