category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

How 5G Affects Test
By Ed Sperling - 11 Nov, 2019 - Comments: 0

David Hall, head of semiconductor marketing at National Instruments, talks with Semiconductor Engineering about architectural changes to infrastructure due to the rollout of 5G and how the move from macrocells to small cells is changing test requirements.         Subscribe to Semiconductor Engineering's YouTube Channel here » read more

Changes In Data Storage and Usage
By Ed Sperling - 09 Oct, 2019 - Comments: 0

Doug Elder, vice president and general manager of OptimalPlus, talks about what’s changing in the storage and collection, including using data lakes and data engineering to break down silos and get data into a consistent format, and why it’s essential to define data up front based upon how quickly it needs to be accessed, as well as who actually owns the data. » read more

Big Shift In AI Perception
By Ed Sperling - 08 Oct, 2019 - Comments: 0

Artificial intelligence, which has been controversial since its inception, is getting a makeover. While fears about massive job displacement and autonomous killing machines will persist, and maybe even grow, AI is being portrayed as a valuable tool for people who know how to harness its capabilities. Underlying all of this is cheap compute and storage, which has made it possible to draw more... » read more

Reducing Costly Flaws In Heterogeneous Designs
By Ed Sperling - 08 Oct, 2019 - Comments: 0

The cost of defects is rising as chipmakers begin adding multiple chips into a package, or multiple processor cores and memories on the same die. Put simply, one bad wire can spoil an entire system. Two main issues need to be solved to reduce the number of defects. The first is identifying the actual defect, which becomes more difficult as chips grow larger and more complex, and whenever chi... » read more

The Single Best DFT Move You Can Make
By Jay Jahangiri - 08 Oct, 2019 - Comments: 0

A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

From Womb To Tomb: A Lifetime Of Chip Data In A Common Language
By Noam Brousard - 08 Oct, 2019 - Comments: 0

Every integrated circuit (IC) has a lifetime of stories to tell. From design through the end of a chip’s life, it can let us know what’s happening all along the way, providing we give it a voice and the language to do so. But until we can gain access to this data, the lives of these ICs remain secret. In-chip monitoring opens up those secrets. It helps to optimize performance, and it is esp... » read more

Shrinking AV’s 1 Billion Test Miles
By Kevin Fogarty - 08 Oct, 2019 - Comments: 0

There is still no answer to how many miles an autonomous vehicle needs to drive before it's proven safe. But some AV developers and test companies are hoping to ease the burden a bit with automation that makes millions of real and simulated miles of road testing simpler to implement, supported by standards that make it easier to create and trade simulation scenarios. The goal is to reduce th... » read more

The Unexpected Impact Of Lots On Hold
By Marie Ryan - 08 Oct, 2019 - Comments: 0

One of the biggest bottlenecks in any Subcon is Lots on Hold. The problem occurs many times a week on most factory floors. It’s something you’ve grown to loathe or endure. But, is there something you can do to reduce the amount of time lots spend on hold? In this article, we will explain what Lots on Hold are and how you can make the process less painful for your team and help improve on-ti... » read more

Testing Against Changing Standards In Automotive
By Ed Sperling and Kevin Fogarty - 08 Oct, 2019 - Comments: 0

The infusion of more semiconductor content into cars is raising the bar on reliability and changing the way chips are designed, verified and tested, but it also is raising a lot of questions about whether companies are on the right track at any point in time. Concerns about liability are rampant with autonomous and assisted driving, so standards are being rolled out well in advance of the te... » read more

Advanced Features Of High-Speed Digital I/O Devices: Data Delay
By NI - 07 Oct, 2019 - Comments: 0

In high speed digital communications, because of factors such as setup time and hold time, it might be important to delay the data from the edge of the clock. The different settings and parameters that affect data delay are discussed in this white paper. To read more, click here. » read more

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