Hierarchical DFT On A Flat Layout Design


The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

Using Better Data To Shorten Test Time


The combination of machine learning plus more sensors embedded into IC manufacturing equipment is creating new possibilities for more targeted testing and faster throughput for fabs and OSATs. The goal is to improve quality and reduce the cost of manufacturing complex chips, where time spent in manufacturing is ballooning at the most advanced nodes. As the number of transistors on a die incr... » read more

Who Is Responsible For Part Average Testing?


With ever-increasing demands in the automotive industry, more and more semiconductor companies are interested in monitoring and improving quality and reliability. Outlier detection and more specifically Part Average Testing (PAT) is the industry standard for the automotive industry. But, who is responsible for quality? Historically, OSATs are responsible for this. In the past, once they... » read more

Yield Impact For Wafer Shape Misregistration-Based Binning For Overlay APC Diagnostic Enhancement


By David Jayez, Kevin Jock, Yue Zhou and Venugopal Govindarajulu of GlobalFoundries, and Zhen Zhang, Fatima Anis, Felipe Tijiwa-Birk and Shivam Agarwal of KLA. 1. ABSTRACT The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pur... » read more

ON Semiconductor Reduces Memory BiST Insertion Time By 6X With Tessent Hierarchical Flow


This paper describes a case study on the insertion of memory BiST for an ON Semiconductor multi-million gate-level netlist with 300 memory instances. The physical implementation will be done using a flat layout. Two different methodologies can be applied when it comes to physical implementation; hierarchical or fullflat. When performing physical implementation as full-flat flow, typically the D... » read more

Big Data Trends Shaping Industry 4.0


In today’s highly competitive economy, automotive OEMs are under pressure to shorten production cycles and fully leverage production capacities, with no compromising of quality and safety. This ebook covers the three big data mega trends for the automotive value chain: ML and AI to streamline processes Actionable Insights Optimized product reliability Don’t lag be... » read more

Advanced Features Of High-Speed Digital I/O devices: Hardware Compare


This paper describes how to use Hardware compare on the NI-HSDIO devices. The hardware compare feature allows users to perform digital comparisons of data on device itself. This allows for real time hardware comparison, which is not possible if data is transferred back to the host computer. This allows for tests such as Bit Error Rate Testing (BERT) and digital waveform comparisons. To read ... » read more

Paving The Way To Autonomous Driving


Over the past couple weeks, four major carmakers began pairing off to jointly develop autonomous vehicles. Numerous reports say Ford will sign a deal with Volkswagen, and BMW is working on Level 4 self-driving vehicles with Daimler, the parent of Mercedes Benz. While this speaks volumes about the enormous cost of developing artificial intelligence systems to drive vehicles, it also points th... » read more

Challenges Of Logic BiST In Automotive ICs


The electronics in passenger cars continues to grow, and much of it is bound by the strict functional safety requirements formalized in the ISO 26262 standard. The ICs that drive the electronics systems in automobiles are also increasingly complex, designed to execute artificial intelligence algorithms that govern emerging self-driving capabilities. Designers are quickly adopting comprehensi... » read more

Silicon Photonics Begins To Make Inroads


Integrating photons and electrons on the same die is still a long way off, but advances in packaging and improvements in silicon photonics are making it possible to use optical communication for a variety of new applications. Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides ar... » read more

← Older posts Newer posts →