category: System-Level Design

category: Auto, Security & Edge AI

Week In Review: Design, Low Power
By Jesse Allen - 13 Mar, 2020 - Comments: 0

Tools & IP Synopsys revealed DSO.ai (Design Space Optimization AI), an autonomous AI application that searches for optimization targets in very large solution spaces of chip design, inspired by the process of DeepMind's game-playing AlphaZero. DSO.ai engines ingest large data streams generated by chip design tools and use them to explore search spaces, observing how a design evolves over t... » read more

Blog Review: Mar. 11
By Jesse Allen - 11 Mar, 2020 - Comments: 0

Rambus' Steven Woo examines how the upcoming deployment of 5G will enable processing at the edge, and how the edge is getting refined further into the near edge and the far edge with a range of AI solutions across it. A Synopsys writer explains the types of Compute Express Link devices and CXL's unique verification challenges like maintaining the cache coherency between a host CPU and an acc... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Mar, 2020 - Comments: 0

Ansys will acquire Lumerical, a developer of photonic design and simulation tools. "The potential of photonics in applications like 5G, IIoT and autonomous vehicles can only be realized by solving immense multiphysics device and system challenges," said James Pond, co-CEO and CTO of Lumerical. "Together, Lumerical and Ansys are uniquely positioned to provide the necessary solutions, and custome... » read more

Banking On FPGA Prototyping
By Ed Sperling - 04 Mar, 2020 - Comments: 0

Juergen Jaeger, product management director at Cadence, explains how FPGA prototyping can improve efficiency and reduce design costs, what the development costs are for various phases of the design flow, how that changes across different markets such as automotive and 5G, and why software is now the biggest knob to turn for reducing cost and time to market. » read more

Blog Review: March 4
By Jesse Allen - 04 Mar, 2020 - Comments: 0

Mentor's Shivani Joshi provides a primer on design rule checks and how they can help flag potential issues in PCB design. Synopsys' Taylor Armerding argues that while better IoT security requires a change in consumer culture and habits, manufacturers and government should be doing more as well. Cadence's Johnas Street chats with several colleagues about what Black History Month means to t... » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages
By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Feb, 2020 - Comments: 0

Tools Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys' automated debug system. Ansys released RaptorH, a tool that com... » read more

Speeding Up FPGA Development
By Ed Sperling - 28 Feb, 2020 - Comments: 0

Salaheddin Hetalani, field application engineer at OneSpin Solutions, talks about why it’s getting harder to design and debug FPGAs, how much design time can be saved through formal techniques, and why just relying on programmability isn’t the most efficient approach. » read more

Chip Design Is Getting Squishy
By Ed Sperling - 27 Feb, 2020 - Comments: 0

So many variables, uncertainties and new approaches are in play today across the chip industry today that previous rules are looking rather dated. In the past, a handful of large companies or organizations set the rules for the industry and established an industry roadmap. No such roadmap exists today. And while there are efforts underway to create new roadmaps for different industries, inte... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy