category: System-Level Design

category: Auto, Security & Edge AI

Efficiency Defines The Future Of Data Movement
By Andy Nightingale - 30 Oct, 2025 - Comments: 0

For decades, chip performance was measured by how much raw compute could be packed onto a die. However, that equation has changed. Moving data across a system-on-chip (SoC) now consumes more energy than the computations it performs. Efficient data movement has become a significant challenge for next-generation SoC designs. AI workloads are multiplying, hyperscale data centers are approaching po... » read more

Even With AI Inroads, Human Chip Designers Still Essential
By Liz Allan - 30 Oct, 2025 - Comments: 0

The proliferation of AI tools seems perfectly matched to fill a talent shortage, but a closer look shows the skills do not entirely overlap. Certain parts of the EDA pipeline require human engineers, and it seems likely to stay that way for the foreseeable future. The dark art of analog design, the final word on safety-critical functional safety, high-level architectural decisions, product i... » read more

Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained
By Felipe Gonçalves - 30 Oct, 2025 - Comments: 0

The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols. What is a Flit Sequence Number? Historically, each TLP carried an explicit sequence number, which, while con... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Siemens EDA - 30 Oct, 2025 - Comments: 0

The importance of reset domain crossing (RDC) verification in ensuring robust and reliable SoC operation cannot be overstated. Verification tools for RDCs are essential in identifying potential metastability issues and ensuring that signal transitions across reset domains are properly handled. This paper presents a novel approach to tackling the challenges of RDC verification involving non-rese... » read more

Advances In Formal Verification Technology
By Brian Bailey - 30 Oct, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Ebook: The Impact of AI On Data Center Design
By Cadence - 29 Oct, 2025 - Comments: 0

AI is reshaping the data center industry. Rising power demands, advanced cooling needs, and digital twin technology are redefining how facilities are designed and operated. Download our free ebook on AI-optimized data centers to learn: How AI workloads are driving massive increases in power and cooling requirements Why liquid cooling is becoming essential for AI infrastructure ... » read more

Blog Review: Oct. 29
By Jesse Allen - 29 Oct, 2025 - Comments: 0

Siemens' Ujjwal Negi and Prashant Dixit warn that while UCIe 3.0 improves performance and efficiency through higher data rates, runtime recalibration, priority sideband messaging, low-power sideband operation, and circular buffer transport, those enhancements also increase verification complexity. Cadence's Anika Sunda suggests that a unified digital thread that connects verification environ... » read more

Developing RISC-V Compute Subsystems
By Baya Systems - 29 Oct, 2025 - Comments: 0

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon processor and Baya’s advanced interconnect tech... » read more

Multiple Challenges Emerge With Physical AI System Design
By Ann Mutschler - 22 Oct, 2025 - Comments: 0

Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, and monitored. Physical AI systems need to work both independently and together. They need the ability to make decisions quickly and locally, typically using much less power than other types of AI... » read more

Blog Review: Oct. 22
By Jesse Allen - 22 Oct, 2025 - Comments: 0

Cadence's Sandip Sadadiya shows what's new in the AMBA AXI Issue L protocol update, which introduces a new credit-based transport mechanism that replaces the traditional VALID/READY handshake, along with improved flow control mechanisms. Siemens' Farhad Ahmed highlights the growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way and intro... » read more

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