category: System-Level Design

category: Auto, Security & Edge AI

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Blog Review: Jan. 30
By Jesse Allen - 30 Jan, 2019 - Comments: 0

Cadence's Paul McLellan provides a primer on embedded memory types, their tradeoffs, and the emerging technologies to keep an eye on. Mentor's Matthew Ballance takes a look at how Portable Stimulus can help create better virtual sequences. Synopsys' Taylor Armerding takes a look at what the next year holds for open source, from changes in license terms to the impact of GDPR and a broader ... » read more

A Simplified Way to Debug IIP Designs and SoC
By Synopsys - 30 Jan, 2019 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Week In Review: Design, Low Power
By Jesse Allen - 25 Jan, 2019 - Comments: 0

M&A Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic's tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company's technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. Th... » read more

Blog Review: Jan. 23
By Jesse Allen - 23 Jan, 2019 - Comments: 0

Synopsys' Taylor Armerding investigates what's happened with the Stuxnet malware since 2010, when it destroyed hundreds of centrifuges at an Iranian nuclear enrichment facility. Cadence's Paul McLellan provides an update on the current state of EUV and what's needed to make high-volume manufacturing possible. In a video, Mentor's Colin Walls explains software's role in embedded system pow... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Jan, 2019 - Comments: 0

M&A Rambus acquired the assets of Diablo Technologies. Founded in 2003, Diablo Technologies specialized in NVDIMM technologies, but was hit with a patent lawsuit by Netlist in 2013. While Diablo won the lawsuit and several subsequent appeals, it declared bankruptcy in December 2017. Rambus says the technology will provide a foundation for integrating existing DRAM and Flash along with emer... » read more

Blog Review: Jan. 16
By Jesse Allen - 16 Jan, 2019 - Comments: 0

Mentor's Harry Foster takes a look at how quickly FPGAs are adopting recent verification techniques, with formal gaining at a rapid pace. Cadence's Paul McLellan checks out the details of two new RISC-V based cores: Western Digital's open source SweRV and Esperanto's Maxion. Synopsys' Taylor Armerding digs into a recent cybersecurity report from the U.S. government and finds a troubling n... » read more

System Bits: Jan. 14
By Jeff Dorsch - 14 Jan, 2019 - Comments: 0

Integrated photonics platform Researchers at Harvard’s John A. Paulson School of Engineering and Applied Sciences came up with an integrated photonics platform capable of storing light and electrically controlling its frequency or color through a microchip. Mian Zhang, first author of the resulting paper, says, “Many quantum photonic and classical optics applications require shifting of op... » read more

Week In Review: Design, Low Power
By Jesse Allen - 11 Jan, 2019 - Comments: 0

M&A QuickLogic acquired SensiML Corporation. Founded in 2017 as a spin-off from Intel, SensiML provides a Software-as-a-Service suite for developing pattern matching sensor algorithms optimized for ultra-low power consumption using machine learning. Details of the deal were not disclosed, though QuickLogic will fund it with shares of common stock. IP CEVA debuted an all-purpose, hybrid... » read more

Blog Review: Jan. 9
By Jesse Allen - 09 Jan, 2019 - Comments: 0

Cadence's Paul McLellan considers the challenges facing copper interconnects as resistance gets harder to deal with and the pros and cons of potential replacement materials. Mentor's Harry Foster digs into how FPGA design and verification engineers spend their time, and why the time designers spend designing has increased. Synopsys' Taylor Armerding contends that the way we use passwords ... » read more

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