category: System-Level Design

category: Auto, Security & Edge AI

MISing In Signoff
By Jim McCanny - 31 Jan, 2019 - Comments: 0

Timing signoff is critical to ensure your design will perform as expected before it is taped out. For many designs, signoff and subsequent ECOs are focused on the performance target and iterating to meet that.  Once the performance goals are met then the attention passes onto hold-time fixing and then, usually, quickly onto tapeout.  However, even after extensive signoff analysis, silicon fai... » read more

Verifying AI Designs Thoroughly And Quickly
By Jean-Marie Brunet - 31 Jan, 2019 - Comments: 0

You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

Using Memory Differently
By Ann Mutschler - 31 Jan, 2019 - Comments: 0

Chip architects are beginning to rewrite the rules on how to choose, configure and use different types of memory, particularly for chips with AI and some advanced SoCs. Chipmakers now have a number of options and tradeoffs to consider when choosing memories, based on factors such as the application and the characteristics of the memory workload, because different memory types work better tha... » read more

Realizing the Benefits of 14/16nm Technologies
By eSilicon - 31 Jan, 2019 - Comments: 0

The scaling benefits of Moore’s Law are challenging below 28nm. It is no longer a given that the cost per gate will go down at process nodes below 28nm, e.g., 20nm though 14nm and 7nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex system-on-chip (SoC) designs is reducing the knowledge base of many chip... » read more

High-Speed Communication Takes A Village
By Mike Gianfagna - 31 Jan, 2019 - Comments: 0

Supply chain, partner network, ecosystem. There are a lot of ways to describe the collection of companies needed to get something done. We’ve all discussed the extensive ecosystem needed to get an advanced chip designed and built. Without a doubt, that is a formidable problem addressed by a sophisticated team of companies. I’d like to take it up a notch in this discussion, however. What abo... » read more

EDA Grabs Bigger Slice Of Chip Market
By Brian Bailey - 31 Jan, 2019 - Comments: 0

EDA revenues have been a fairly constant percentage of semiconductor revenues, but that may change in 2019. With new customers creating demand, and some traditional customers shifting focus from advanced nodes, the various branches of the EDA tool industry may be where sticky technical problems are solved. IC manufacturing, packaging and development tools all are finding new ways to handle t... » read more

Chips&Media: Design and Verification of Deep Learning Object Detection IP
By Mentor, a Siemens Business - 30 Jan, 2019 - Comments: 0

Chips&Media, a leading provider of high-performance video IP for SoC design, took a unique approach to designing their latest IP for detecting objects in real time. They decided to adopt a new High-Level Synthesis (HLS) flow to implement their deep learning algorithm. But, they would have an RTL team create this algorithm, using traditional tools and another team would employ the Catapult H... » read more

Shifting the Burden of Tool Safety Compliance from Users to Vendor
By OneSpin Solutions - 30 Jan, 2019 - Comments: 0

The security, safety and performances of autonomous vehicles, railways, aerospace, nuclear power plants and medical devices rely on electronic systems and their hardware components. Engineers use advanced software tools to develop complex hardware. Tools may malfunction, generate erroneous output and ultimately introduce or fail to detect systematic hardware faults that could cause hazardous ev... » read more

Clock Domain Crossings in the FPGA World
By Aldec - 30 Jan, 2019 - Comments: 0

Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC issues on design functionality grows even more. This paper outlines CDC issues and their solutions for FPGA designs. Various design techniques are presented together with real-life examples for Xilinx and Intel FPGA devices. More import... » read more

Blog Review: Jan. 30
By Jesse Allen - 30 Jan, 2019 - Comments: 0

Cadence's Paul McLellan provides a primer on embedded memory types, their tradeoffs, and the emerging technologies to keep an eye on. Mentor's Matthew Ballance takes a look at how Portable Stimulus can help create better virtual sequences. Synopsys' Taylor Armerding takes a look at what the next year holds for open source, from changes in license terms to the impact of GDPR and a broader ... » read more

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