category: System-Level Design

category: Auto, Security & Edge AI

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

Tech Talk: Improving Verification
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018
By Frank Schirrmeister - 26 Apr, 2018 - Comments: 0

Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

EDA In The Cloud
By Brian Bailey - 26 Apr, 2018 - Comments: 4

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Multi-Die Packaging And Thermal Superposition Modeling
By eSilicon - 25 Apr, 2018 - Comments: 0

Packaging density, electrical performance and cost are the primary factors driving electronic package architectures for high-performance server markets. Considerations such as thermal performance and mechanical reliability are equally important but tend to be addressed later in the design cycle. Presented in this paper is a historical view of the packaging trends leading to the current multi-di... » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs
By Aldec - 25 Apr, 2018 - Comments: 0

This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

8 Checks That Every PCB Designer Needs To Achieve Electrical Sign-Off
By Mentor, a Siemens Business - 25 Apr, 2018 - Comments: 0

Automate electrical design rule checking (DRC) for fast, cost-effective PCB design verification. These eight rules apply regardless of your PCB layout tool or level of expertise. To read more, click here. » read more

Synopsys’ Vision For The New Wave Of Chip Design
By Synopsys - 25 Apr, 2018 - Comments: 0

Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Blog Review: Apr. 25
By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

System Bits: April 24
By Ann Mutschler - 24 Apr, 2018 - Comments: 0

Some superconductors carry spin currents A few years ago, researchers from the University of Cambridge showed that it was possible to create electron pairs in which the spins are aligned: up-up or down-down. The spin current can be carried by up-up and down-down pairs moving in opposite directions with a net charge current of zero, and the ability to create such a pure spin super-current is an... » read more

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