IC Validator Programmable EERC Netlist Domain Checking Technology


Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper introduces IC Validator programmable Extended Electrical Rule Checking (EERC) and categorizes electrical rule checking (ERC) into th... » read more

Blog Review: July 27


Mentor's Tom Fitzpatrick investigates how to add new behavior to an existing testbench with the UVM factory class. Synopsys' Srinivas Vijayaragavan and Pooja Gupta dig into new features of SAS 24G, including how its effective speed was doubled to 24G though signaling rate remains at 22.5G. Cadence's Paul McLellan highlights a presentation from the SEMI/Gartner Market Symposium focused on ... » read more

Formal Analysis Of X Propagation


Verifying the absence of undefined signal values in a design is in general a hard problem. Formal 4-state logic analysis offers a powerful solution. This white paper discusses X-related verification issues, and how advanced 4-state formal analysis solves them. This white paper covers the 360 DV-Verify product. To read more, click here. » read more

System Bits: July 26


Mixing topology, spin MIT researchers are studying new compounds, such as topological insulators (TIs), which support protected electron states on the surfaces of crystals that silicon-based technologies cannot as part of the pursuit of material platforms for the next generation of electronics. They report new physical phenomena being realized by combining this field of TIs with the subfiel... » read more

Leading Chip Maker Rolls Out SoC For Automotive Market With NetSpeed Gemini


There is tremendous growth in the automotive IC market due to the trend towards electric or hybrid cars and applications for enhanced safety. However, the technical challenges of implementing today's connected car and the autonomous vehicles of the future are daunting. To read more, click here. » read more

Enhancing Verilog Designs With Embedded PSL


PSL (Property Specification Language) is one of the easiest introductions to the world of design properties, assertions and coverage points to anybody familiar with Verilog HDL. The designer of a digital circuit has the best understanding of the operation of the circuit, which makes her or him the best person to define properties that will fire assertion messages in case of incorrect design beh... » read more

Introduction to the Compute Express Link Standard


By Gary Ruggles, Sr. Product Marketing Manager, Synopsys Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a Host and Device is required. A consortium to enable this new standard was recently announced simultaneously with the release of the CXL 1.0 specification. Th... » read more

The Week In Review: Design


Tools Synopsys updated its static timing analysis tool to use smart engineering change order (ECO) technology, which the company says reduces memory requirements by 5X and speeds runtime by 2X. The release also allows more scenarios on a single server, or flexible distribution to take advantage of customers' private compute clouds. IP Synopsys released MIPI display and camera interface... » read more

Blog Review: July 20


Applied's Er-Xuan Ping addresses the challenges facing materials and processing in a changing memory landscape, and the opportunities that may arise. Cadence's Paul McLellan looks at teaching neural networks to perceive things more like humans do, through German traffic signs. Mentor's Colin Walls digs into managing timing and peripherals in embedded systems. Synopsys' Robert Vamosi ch... » read more

Can Verification Meet In The Middle?


Semiconductor Engineering sat down to discuss these issues with; Stan Sokorac, senior principal design engineer for [getentity id="22186" comment="ARM"]; Frank Schirrmeister, senior group director for product marketing for the system development suite of [getentity id="22032" e_name="Cadence"]; Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor Graphics"], Bernie... » read more

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