category: System-Level Design

category: Auto, Security & Edge AI

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

Beyond UVM Registers — Better, Faster, Smarter
By Mentor, a Siemens Business - 27 Jan, 2016 - Comments: 0

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex syst... » read more

Debug: Last Bastion Of Automation
By Brian Bailey - 27 Jan, 2016 - Comments: 0

There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Finding CDC Issues Before They Find You
By Aldec - 27 Jan, 2016 - Comments: 0

Clock domain crossings (CDCs) in FPGAs represent a probabilistic opportunity for failure. Functional simulation and static timing analysis tools are insufficient. Finding and addressing metastability and data incoherence around CDCs require static and dynamic analysis of FPGA designs. Aldec ALINT-PRO-CDC provides enhanced confidence that CDCs are located and fully mitigated. To read more, cl... » read more

Blog Review: Jan. 27
By Jesse Allen - 27 Jan, 2016 - Comments: 0

There's an ocean of possibilities for transistors and interconnects at the 5nm node, says Cadence's Paul McLellan – but will any of them be feasible in time? How would you design R2-D2? Mentor's Joe Hupcey III lays out what low power techniques he thinks the Star Wars droid might require. It's not all clear skies in the world of FinFETs, as Synopsys' Graham Etchells continues his series... » read more

System Bits: Jan. 26
By Ann Mutschler - 26 Jan, 2016 - Comments: 0

Precisely controlling graphene molecules Researchers at UCLA’s California NanoSystems Institute have found that in the same way gardeners may use sheets of plastic with strategically placed holes to allow plants to grow but keep weeds from taking root, the same basic approach can be applied in terms of placing molecules in the specific patterns they need within tiny nanoelectronic devices, w... » read more

The Week In Review: Design/IoT
By Jesse Allen - 22 Jan, 2016 - Comments: 0

Tools Synopsys unveiled its comprehensive standard cell library characterization and QA solution, SiliconSmart ADV, highlighting a simple multi-core licensing scheme for easy adaptation to constantly changing characterization workload requirements. Cadence updated its Sigrity portfolio focusing on multi-gigabit interfaces, including automated support for IBIS-AMI model creation, channel m... » read more

Blog Review: Jan. 20
By Jesse Allen - 20 Jan, 2016 - Comments: 0

How far can you go on solar power? 493 million miles, at least if you're the Juno spacecraft. Plus, winemaking gets a boost from submarine technology, in this week's top tech picks from Ansys' Bill Vandermark. Mentor's Steve Pateras digs into how automotive ICs bring a whole new set of requirements that are driving the evolution of memory BIST. If you're interested in neural networks and ... » read more

System Bits: Jan. 19
By Ann Mutschler - 19 Jan, 2016 - Comments: 0

Electromagnetic properties of graphene-boron nitride materials Rice University and Montreal Polytechnic researchers reported that developing novel materials from the atoms up goes faster when some of the trial and error is eliminated. The work aims to simplify development of certain exotic materials for next-generation electronics. Specifically, Rouzbeh Shahsavari, a Rice materials scient... » read more

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