category: System-Level Design

category: Auto, Security & Edge AI

Is Formal Ready To Displace Simulation?
By Brian Bailey - 21 May, 2014 - Comments: 2

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In part two, the panel focused on the subject of coverage and the ways in which formal coverage can be combined with simulation. In this segment we start exploring the impact that sequential equi... » read more

FinFET And Multi-Patterning Aware Place And Route Implementation
By Mentor, a Siemens Business - 21 May, 2014 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Olympus-SoC place and route system handles them. To view this white paper, click here. » read more

Tech Talk: Silicon Photonics
By Ed Sperling - 21 May, 2014 - Comments: 2

Mentor Graphics' John Ferguson explains why light is getting so much attention for inter-chip communications, where it excels, and why it has limitations. This is the first part in a two-part series. [youtube vid=0ydkDmrSrF4] » read more

Using Virtual Prototypes To Address The Growing Software Complexity In Automotive
By Synopsys - 21 May, 2014 - Comments: 0

The software content is growing steadily across multiple applications and the automotive market is no exception to this. In fact the amount of electronics and software in cars is transforming the way we perceive the value of a car. With this steady increase in software also comes the need to handle the amount and the complexity of all these different software stacks. And unlike other applicatio... » read more

Blog Review: May 21
By Ed Sperling - 21 May, 2014 - Comments: 0

Mentor’s Colin Walls offers up some new insights into C++ exception handling, thanks to some input from colleague Jonathan Roelofs. This one involves minimizing overhead and reducing runtime penalties. Synopsys’ Mick Posner is back in the saddle again—literally. This is about as green as it gets. Cadence’s Arthur Marris reports back on the IEEE 802.3 Ethernet standards meeting, in... » read more

Engineering For Next-Gen Memory Performance
By Katherine Derbyshire - 20 May, 2014 - Comments: 0

When only a few electrons mean the difference between the ON and the OFF state, it’s difficult to manufacture [getkc id="22" kc_name="memory"] elements with consistent, reliable performance. This is the situation conventional capacitance-based memories face as critical dimensions drop to just a few nanometers. As a result, device designers are considering a wide range of alternative memory... » read more

System Bits: May 20
By Ann Mutschler - 20 May, 2014 - Comments: 0

Re-routing noise away from measurement Today, we are capable of measuring the position of an object with unprecedented accuracy, but quantum physics and the Heisenberg uncertainty principle place fundamental limits on our ability to measure. Noise that arises as a result of the quantum nature of the fields used to make those measurements imposes what is called the "standard quantum limit," whi... » read more

Taming The PDK Beast At DAC
By Steve Schulz - 19 May, 2014 - Comments: 0

A quick Web search on the phrase “process design kit” reveals about 48 million matches. This happens to be about 10 times larger than for the current pop dance sensation “twerking,” so I guess that’s at least something to brag about. Yet if we now add the word interoperability to our PDK search, we find only 200K matches, or less than 0.5% — and therein exposes the chronic problem w... » read more

The Week In Review: Design
By Ed Sperling - 16 May, 2014 - Comments: 0

M&A Synopsys’ Coverity subsidiary bought Kalistick, a French company that makes cloud-based solutions to boost testing efficiency by allowing engineers to identify and prioritize tests. Terms of the deal were not disclosed. Tools Cadence rolled out verification IP for the new PCI Express 4.0 architecture. The new spec supports up to 16 billion transactions per second, which is double... » read more

Blog Review: May 14
By Ed Sperling - 14 May, 2014 - Comments: 0

Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Of particular note is element No. 117, a new entry in the periodic table. The temporary name is ununseptium, which means…well, surprise…117. Cadence’s Brian Fuller follows a panel discussion about the biggest potential roadblock for the IoT’s success—privacy and security. You’ve been warned. Syn... » read more

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