Security Tradeoffs In A Shifting Global Supply Chain


Experts at the Table: Semiconductor Engineering sat down to discuss a wide range of hardware security issues and possible solutions with Norman Chang, chief technologist for the Semiconductor Business Unit at ANSYS; Helena Handschuh, fellow at Rambus, and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that conversation. The first part of this discussion ca... » read more

Open ISAs Gaining Traction


Open instruction set architectures are starting to gain a foothold, often in combination with other processors, as chipmakers begin to add more specialized compute elements and more flexibility into their designs. There are a number of these open ISAs available today, including Power, MIPS, and RISC-V, and there are a number of permutations and tools available for sale based on those archite... » read more

The Growing Impact Of Portable Stimulus


It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Why Data Is So Difficult To Protect In AI Chips


Experts at the Table: Semiconductor Engineering sat down to discuss a wide range of hardware security issues and possible solutions with Norman Chang, chief technologist for the Semiconductor Business Unit at ANSYS; Helena Handschuh, fellow at Rambus, and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that conversation. The first part of this discussion ca... » read more

The Race To Next-Gen 2.5D/3D Packages


Several companies are racing each other to develop a new class of 2.5D and 3D packages based on various next-generation interconnect technologies. Intel, TSMC and others are exploring or developing future packages based on one emerging interconnect scheme, called copper-to-copper hybrid bonding. This technology provides a way to stack advanced dies using copper connections at the chip level,... » read more

Challenges Grow For Finding Chip Defects


Several equipment makers are developing or ramping up a new class of wafer inspection systems that address the challenges in finding defects in advanced chips. At each node, the feature sizes of the chips are becoming smaller, while the defects are harder to find. Defects are unwanted deviations in chips, which impact yield and performance. The new inspection systems promise to address the c... » read more

Magnetic Memories Reach For Center Stage


Wearable heart rate sensors. Networked smoke detectors. Smart lighting. Smart doorbells. While desktop computers and even smartphones are powerful standalone tools, Internet of Things devices share a need to collect data from the environment, store it, and transmit it to some other device for action or further analysis. In many systems, data storage and working memory account for the majorit... » read more

Using Machine Learning In Fabs


Amid the shift towards more complex chips at advanced nodes, many chipmakers are exploring or turning to advanced forms of machine learning to help solve some big challenges in IC production. A subset of artificial intelligence (AI), machine learning, uses advanced algorithms in systems to recognize patterns in data as well as to learn and make predictions about the information. In the fab, ... » read more

Why DRAM Won’t Go Away


Semiconductor Engineering sat down to talk about DRAM's future with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of that conversation. Part ... » read more

EDA Revenue Up 6.6% For Q2


Highlighted by double digit growth in semiconductor IP and the Asia/Pacific region, EDA industry revenue increased 6.6% for Q2 2019 to $2,472.1 million, compared to $2,318.5 million in Q2 2018, according to the ESD Alliance Market Statistics Service. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 6%, which represented a... » read more

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