Improving the thermal properties and reliability of FCLBGA packages.
In recent years, rapid technological advancements in the field of high-performance computing have driven the development of increasingly sophisticated and powerful computing devices. This growth is expected to continue, with expansion into areas such as central processing units (CPUs), artificial intelligence (AI) systems, and automotive products.
Flip chip lidded ball grid array (FCLBGA) packaging technology, which is commonly used in high-performance computing applications, is faced with significant challenges from a heat dissipation perspective. Effective thermal management is a crucial factor in maintaining optimal performance and preventing overheating, which can lead to a reduction in reliability and a deterioration in performance. Therefore, the use of materials with high thermal conductivity has been actively investigated to improve the thermal properties of FCLBGA packages.
There is a growing requirement for the development of advanced materials and technologies, including indium metal thermal interface materials. Indium exhibits excellent thermal conductivity, high adhesion to devices and durability. Therefore, indium metal thermal interface materials (TIMs) are expected to play an important role as thermal management solutions in high-performance semiconductors and electronic devices.
However, in FCLBGA packaging, the melting point of indium is lower than the reflow temperature for solder ball attach, which results in low thermal interface material coverage due to the re-melting of the indium and flow of the TIM in the liquid phase. This issue has a significant impact on the overall thermal performance and reliability of the package. To address this issue, it is important to study indium alloys with different melting points, investigate the causes of reduced TIM coverage due to low melting point, and explore ways to improve package reliability. This study aims to analyze the causes of the problem and propose strategies to improve package reliability through the development of advanced materials.
The Joint Electron Device Engineering Council (JEDEC), an organization that sets standards for semiconductors and electronic components, specifies various qualification conditions for the reliability testing of semiconductor packages such as flip chip ball grid array (FCBGA) packages. Reliability test conditions, multiple reflow test (MRT, L4/245°C), highly accelerated stress test (HAST, 85% RH, 130°C 96 hours), temperature cycling B (T/C B, -55 to +125°C for 1000 cycles) and a high temperature storage (HTS) test (150°C for 1000 hours), are commonly used to evaluate the reliability of FCBGA packages. Each condition is set to ensure the thermal, mechanical, and environmental reliability of the package.
In this study, the Moisture Sensitivity Level (MSL) L4 condition (reflow within 72 hours at 30°C/60% relative humidity) was adopted for preconditioning to evaluate the moisture sensitivity of the package after the packaging process. In addition, a multiple reflow test was conducted to simulate the board-level process and determine how well the semiconductor package can withstand various temperature changes and stresses that may be encountered in the actual use environment.
FCBGA products undergo a total of four reflows in the chip scale reliability test, including the solder ball attach process (once) and the MRT test (three times). Due to the lower melting point of indium alloy compared to the reflow temperature, re-melting can occur during these processes, potentially leading to TIM void issues. However, the reliability evaluation in this paper was conducted at the chip scale, which may be different from the actual conditions of board mounting.
Additionally, previous studies have confirmed that there is little change in TIM coverage as HTS and HAST progress, so only the temperature cycling test was performed in this study.
In general, FCBGA packaging adopts the T/C B (-55°C to +125°C) or T/C C (-65°C to +150°C) condition to check the mechanical stress or physical properties of the material in a low temperature environment (-55°C or -65°C), but T/C B or C conditions may be too harsh to be applied to devices used in this field because devices with high heat dissipation, especially servers or network equipment, are always exposed to a high temperature environment, which requires a TIM with high thermal conductivity such as an indium metal TIM. Therefore, this study applied T/C K conditions (0°C to 125°C) and observed whether there is any change in TIM coverage after 500 cycles and 1000 cycles using 2 cycles per hour.
TIM1 is used to fill the microscopic gaps between the silicon chip and the heat spreader. By doing so, the TIM reduces thermal resistance and optimizes the path for heat to flow out of the device. The more extensive and uniform the TIM coverage, the more efficient heat can be transferred away from the device. Conversely, insufficient or uneven TIM coverage can increase thermal resistance, leading to higher device temperatures.
Inadequate thermal dissipation can cause a device to overheat, which may degrade performance and reduce its lifespan. For instance, an overheated semiconductor chip can suffer from performance throttling or permanent damage. Adequate TIM coverage ensures efficient heat dissipation, helping maintain device performance and reliability. Therefore, this study aimed to verify the TIM coverage of each indium alloy at the process step after heat spreader attach and after reliability test. To verify the TIM coverage of the indium metal TIM, SAT non-destructive testing was performed, utilizing T-Scan.
A C-Scan provides a single interface at a specific depth in a 2D image, which is useful for detecting defects or non-uniformities at that layer, and it is also often used to check the TIM coverage of polymer TIMs. Because it focuses only on a specific depth, it is limited in its ability to simultaneously identify problems at multiple interfaces in a multi-layer structure, and it is difficult to accurately confirm the problem of TIM coverage degradation between the die and heat spreader.
In contrast, a T-Scan provides 3D information by continuously scanning multiple interfaces along the full thickness of the specimen. Although T-scan has lower resolution compared to C-scan in inspecting specific areas, it is more advantageous for detecting delamination across multiple layers (see Figure 1). Therefore, this paper attempts to evaluate the TIM coverage more accurately by using SAT images with T-Scan, calculating the TIM coverage with the Void Analyzer program, and quantifying the change in TIM coverage according to the reliability test results.
Fig. 1: TIM coverage image comparison: (a) C-scan image and (b) T-scan image. In the C-scan image, the black spots indicate sufficient TIM coverage, while in the T-scan image, they represent voids or delamination.
To check the warpage of the package vs. temperature range, the BGA area of the package completed to the end of line (EOL) process was set as the region of interest (ROI) for performing the shadow moiré analysis. The shadow moiré process was set between room temperature (RT) to 260°C to check the change in package warpage when the package is exposed to the typical reflow soldering process temperature. Three cycles were performed to check the reproducibility of package deformation due to repeated thermal stress.
In this study, the warpage behavior of packages subjected to the heat spreader attach process at room temperature and high temperature (HT), with a solder reflow temperature of 260°C using five different types of indiums, was simulated to determine the correlation of TIM coverage degradation with the warpage behavior of the package subjected to the reflow process.
For the simulation, the following approach was considered:
SEM is an instrument that uses an electron beam to observe the surface of a sample with extremely high resolution. After reliability tests, SEM inspection was performed to check microstructure of indium alloy TIM and interface quality.
In this study, the test vehicle used for the evaluation of the indium alloy is a flip chip lidded ball grid array (FCLBGA) (see Figure 2) with a 52.5 x 52.5 mm package size, a 25.6 x 25.6 mm die size and a gold (Au) backside metallization process applied to the die and heat spreader side after wafer back grinding to enhance the TIM solderability.
Fig. 2: FCLBGA package structure.
A phase diagram visually represents the phases (solid, liquid, or a mixture of both) that exist based on the alloy’s composition and temperature. It helps to understand phase transformations as temperature and composition change, and allows for determining the melting temperature, solidification range and the proportion of solid and liquid phases. Interpretation of the phase diagram of the indium-silver alloy shows that the liquidus temperature decreases as the silver content decreases. Based on these characteristics, this study investigates the TIM coverage trends for five different compositions with varying levels of silver content within the shade of red in Figure 3. The indium-silver alloy candidates were named in order of decreasing silver content as A, B, C, D, and E. Specifically, the alloy with the highest silver content was named A, and the next highest, B.
Fig. 3: Silver-indium phase diagram. Five different indium-silver alloys were selected from the shaded red area.
The test vehicles were processed in accordance with the procedure shown in Figure 4. This process flow chart outlines the key processes of FCLBGA with an indium metal TIM from wafer incoming to final assembly. In this study, the experiments were specifically focused on the heat spreader attach process that used a fluxless method.
Fig. 4: Assembly process flow for an FCBLGA with an indium metal TIM.
The results (see Figure 5) showed a trend comparison of TIM coverage degradation by indium-silver alloy after EOL and MRT. The TIM coverage (%) was measured based on T-scan images to understand the influence of TIM coverage on each readout. It was found that the greatest TIM coverage degradation was caused from alloy E after EOL and MRT when solder reflow temperature was applied. Although there is a slight deviation, indium alloys with lower silver content tend to be more affected by solder reflow temperatures and more delamination was confirmed in the die edge area.
Fig. 5: TIM coverage degraded after EOL and MRT L4. TIM coverage degradation results are normalized to alloy A.
Figure 6 shows the summary of the TIM coverage results with T-scan readouts after processes and reliability tests. All alloys showed >90% TIM coverage even after T/C K 1000X. Alloys D and E with lower silver content showed higher TIM coverage degradation than the others.
Fig. 6: TIM coverage per read out (T-scan). The red box indicates silicon die outline. A black spot in a red box indicates TIM coverage degradation due to a void or delamination.
To study the package warpage with temperature, the warpage from RT to HT (solder reflow peak temperature of 260°C) was monitored, and it was found that the lower the silver content of the indium alloy, the greater the warpage magnitude between RT and HT in the die area (see Figure 7). These results may be related to the greater degradation of TIM coverage with lower silver content, as seen in the previous section.
Fig. 7: Shadow Moiré result (2D/3D plot). ROI: BGA side of package with heat spreader.
In this study, the warpage of the package and die at room temperature and high temperature was simulated by FEA. Tests revealed that the largest warpage occurs in the corner area of both the PCB and the die, as shown in Figure 8. Furthermore, the die warpage tends to be worse (smile mode) at HT (see Figure 9). The warpage at HT of the package and die gets worse (see Figure 9 and 10) and the difference in magnitude between RT & HT gets higher (see Figure 11.) as the silver content in the indium alloy decreases.
Fig. 8: 3D contour without heat spreader (top view).
In conclusion, the simulation results were similar with the shadow Moiré result. The lower the silver content, the greater the magnitude of the warpage was between RT and HT, and alloy E with the lowest silver content showed the greatest warpage from the FEA simulation results.
Fig. 9: Simulation result of normalized signed warpage of the package. Simulation results are normalized to the simulation with alloy E. Yellow and green curves indicate the package warpage behavior at RT and HT, respectively.
Fig. 10: Simulation results of normalized (to alloy E) die corner strain.
Fig. 11: Simulation result of die warpage values on die at room temperature (25°C) and high temperature (260°C). Each curve in this figure indicates a visualization of the signed die warpage values on die from Figure 10, mapped to the shape of the die, with curves shown for both RT and HT.
A cross-section and SEM inspection were conducted to investigate the delamination aspect of the test material identified as having die edge delamination through SAT (T-scan). The alloy E material, which exhibited significant die edge delamination after T/C K 1000X, was selected for analysis. Delamination was observed at the die-TIM interface at both ends of the die (see Figure 12), which is consistent with the findings from the T-scan. This confirmed the effectiveness of the T-scan for monitoring metal TIM delamination.
Fig. 12: SEM inspection results of the alloy A cross section after T/C K 1000X: (a) delamination on the left end of the die and (b) delamination on the right end of the die.
This study investigated the effects of the silver content of indium metal TIMs on package warpage and its relationship to TIM coverage degradation. Based on the evaluation of TIM coverage for each read-out after reliability testing, warpage as assessed by shadow moiré, and warpage and simulation results from FEA, reducing the silver content in the indium alloy results in greater TIM coverage degradation and increased package and die warpage at high temperatures. These results highlight the need to control silver content in package design and TIM selection to ensure reliable performance. In addition, FCLBGA packages were subjected to multiple reflow temperatures during the assembly process, and the indium alloy re-melted due to its lower liquidus temperature than the solder reflow temperature. This process affects the warpage behavior, causing more strain in the die corner area. This can lead to TIM coverage degradation.
Considering these findings, it may be advantageous in terms of TIM coverage to use an indium alloy with a higher silver content for FCLBGA packages undergoing solder reflow. However, this assumption is only valid for FCLBGA packages with large warpage deflection at room temperature and high temperature. Future research on each alloy will need to focus on practical measures to further reduce package warpage and maintain TIM coverage.
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