Dizzying number of options emerge, but cost remains key factor.
Amid a challenging business environment, the outsourced semiconductor assembly and test (OSAT) industry is projected to see steady to strong growth in a number of packaging segments this year.
Right now, the OSATs—which provide third-party IC-packaging and test services—are seeing brisk demand for both legacy and advanced chip packages. In addition, IDMs continue to outsource more of their packaging production to the OSATs, which is fueling the growth in the OSAT sector.
Despite uncertainty in the worldwide economic and political climate, the OSATs are upbeat. “We are optimistic,” said Tien Wu, chief operating officer for Taiwan’s Advanced Semiconductor Engineering (ASE), the world’s largest OSAT. “We are seeing that the market conditions are continuing to improve, at least for the 2017 outlook. We are seeing strength in all sectors.”
In total, the OSAT industry is projected to grow by 5% to 6% in terms of revenue in 2017 over 2016, according to Sebastian Hou, an analyst at CLSA, an investment banking firm. In 2016, the OSAT market grew by 6%, according to CLSA. The figures represent the total IC-packaging and test revenues from the OSATs.
The numbers don’t tell the entire story, however. Here are some of the major trends in the OSAT business:
“2016 was actually a milestone for the packaging industry,” Wu said. “In 2016, the InFo from TSMC reconfirmed how fan-out can be adopted to improve the packaging part of the performance and the system-level performance.”
Apple’s move to adopt fan-out packaging is also prompting the OSATs to race each other and develop similar packages for smartphones and other applications. But most other smartphone OEMs haven’t jumped on the fan-out bandwagon—yet. Fan-out provides more I/Os than existing solutions, but it’s also more expensive.
The uncertainty whether fan-out will gain broad adoption could create a “fan-out bubble” in the industry, according to Yole Développement, a market research firm.
Still, the growth in the OSAT market isn’t dependent on fan-out alone. System-in-package (SiP) and other segments are also projected to grow in 2017. Used in various systems, SiP integrates multiple dies in a single package. “The revenue growth rate for the OSAT industry is expected to be higher going forward, driven by the emerging demand for SiP solutions,” said Scott Sikorski, vice president of product technology marketing at STATS ChipPAC, a member of the JCET group of companies.
To be sure, the OSAT and packaging landscapes are complicated. To help the industry gain an insight into what’s ahead, Semiconductor Engineering has taken a look at the OSAT business and various packaging markets, such as 2.5D/3D, SiP, wafer-level packaging (WLP) and wirebond.
OSAT landscape
Basically, there are three entities that develop chip packages and provide test services—OSATs, foundries, and integrated device manufacturers (IDMs).
The OSATs are merchant vendors. Today, there are more than 100 different OSATs in the market. But roughly 10 OSATs make up more than 75% of the total sales in the business, according to TechSearch International.
Many IDMs develop chip packages for their own IC products. Meanwhile, some foundries, such as Intel, Samsung and TSMC, provide chip packaging and test services for customers. In contrast, most foundries don’t develop chip packages for customers. Some foundries provide some level of manufacturing services in the arena.
IDMs and foundries with internal packaging operations also outsource a certain percentage of their IC-packaging production to the OSATs. Generally, they don’t have the capacity to produce everything. And needless to say, the fabless companies also outsource their packaging to the OSATs and/or foundries.
In total, the combined IC-packaging and test service market, which includes OSATs, foundries and IDMs, is projected to reach $53.3 billion in 2017, up 7% from $49.8 billion in 2016, according to Gartner.
Of that figure, the IDM’s in-house packaging and test sector are projected to have a combined dollar value of $25.2 billion in 2017, up from $23.9 billion in 2016, according to Gartner. And in total, the OSAT’s packaging and test revenue is projected to reach $28.1 billion in 2017, up from $25.9 billion in 2016, according to Gartner.
Gartner’s OSAT forecast is slightly different than others, as it predicts the business will grow by 8.5% in 2017. In 2016, the OSAT business grew 1.4%. Meanwhile, the overall IC market is projected to grow by 7.2% in 2017, compared to 1.5% growth in 2016, according to the firm.
In total, capital spending for the OSATs alone is expected to reach $2.4 billion in 2017, down 10% from 2016, according to Pacific Crest Securities. Among the larger OSATs, though, ASE’s capital spending is expected to be higher in 2017 over 2016. Amkor’s capital spending is expected to be flat. The big spender is China’s JCET group, which plans to boost its capital spending by 20% in 2017.
Obviously, the forecasts could change this year amid uncertainty in the economic climate. What hasn’t changed is that the OSAT market is a tough and competitive business with lower margins. Customers want the OSATs to cut their packaging prices by 2% to 5% every year.
Amid the margin pressures, OSATs have also seen an increase in R&D costs, particularly in the development of advanced packaging. Fewer OSATs can afford to make the necessary investments in advanced packaging. “It’s getting tougher and tougher,” said E. Jan Vardaman, president of TechSearch. “In order to put the CapEx in, you must have a bigger revenue base. The investments that you are making are also more expensive.”
In advanced packaging, for example, the OSATs must buy a different and expensive set of tools that aren’t typically used in most packaging flows. “They are more like wafer fab equipment,” Vardaman said.
The increase in R&D costs is fueling a wave of merger and acquisition activity in the arena. OSATs need to pool their resources to develop expensive package types. Moreover, the OSATs are consolidating for other reasons. “The customers are consolidating,” ASE’s Wu said. “That will continue in the semiconductor industry. That will drive the supply chain to have more consolidation, especially in packaging.”
Among the OSATs, ASE, Amkor and China are the most active players in the merger and acquisition arena. Here are the latest business deals:
What happened to 2.5D?
On the technology front, meanwhile, there are a plethora of packaging types. No one package can meet all requirements. “Packaging is a highly customized business based on end applications,” said Raman Achutharaman, corporate vice president and general manager of the Etch Business Unit at Applied Materials.
From Achutharaman’s standpoint, packaging can be divided into three main categories—high-end technologies like 2.5D/3D; mid-range like SiP and WLP; and low-cost like wirebond.
For years, the industry has been working on 2.5D, a die stacking technique that promises to boost the bandwidth in devices. 2.5D involves several pieces—a package, interposer with through-silicon vias (TSVs), and dies. The package is on the bottom while the dies are on top. The interposer is the bridge between them. Interposers have TSVs, which act as fast electrical signal conduits between the package and dies.
Fig. 1: 2.5D HPC system with GPU, HBM2 and interposer. Source: Nvidia.
2.5D and a related technology, 3D, make sense. It becomes economically harder to justify putting everything on a single system-on-chip (SoC) amid soaring design and manufacturing costs at leading-edge nodes. “The cost of meeting Moore’s Law is increasing and the demand for performance is increasing. A portion of the roadmap now requires multi-die modules,” said David McCann, vice president of packaging R&D and operations at GlobalFoundries.
So far, 2.5D has gained traction in high-end applications, such as FPGAs, graphics chips and networking applications. The big issue with 2.5D is cost. This has kept 2.5D from becoming a more mainstream technology. Still, the market for TSV technology will grow at an annual rate exceeding 10% over the next five years, according to Yole.
“TSV or 2.5D packages will see only a slight increase in usage with new products entering the market in the graphics arena,” said Ron Huemoeller, vice president of worldwide R&D at Amkor. “The 2.5D package space in terms of revenue will remain relatively flat in 2017 with primary usage in the high-end networking markets.”
Still, the industry is expected to roll out new 2.5D technologies in 2017. “There are new designs with silicon interposers,” TechSearch’s Vardaman said. “The high-performance packaging companies are looking for ways to drive down cost.”
Walter Ng, vice president of business management at UMC, added: “The interest in interposer and TSV will continue. That is still an evolving technology arena.”
What is SIP and WLP?
Today, meanwhile, the buzz revolves around fan-out packaging. In total, the fan-out market is expected to grow from $244 million in 2014 to $2.5 billion by 2021, according to Yole.
WLP involves packaging an IC while it’s still on the wafer. Basically, WLP involves two technologies—chip-scale packaging (CSP) and fan-out. In fan-out, individual dies are embedded in an epoxy material. The interconnects are fanned-out in the package, enabling more I/Os. Fan-out does not have an interposer, making it cheaper than 2.5D.
The first wave of fan-out packages, called embedded wafer-level ball-grid array (eWLB), appeared in 2009. Generally, eWLB are lower-density packages with fewer I/Os.
Today, TSMC and the OSATs are developing or shipping high-density fan-out packages, which support more I/Os. In addition, there are several different types of fan-out technologies.
One big market for fan-out is smartphones. Traditionally, smartphone OEMs have incorporated a technology called package-on-package (PoP). In PoP, a memory package is stacked on top of an application processor package. PoP is reliable and cheap, but it runs out of steam at thicknesses of 0.5mm to 0.4mm.
For that reason, Apple moved from PoP in its previous iPhones to TSMC’s fan-out package in the iPhone 7. But not all smartphone OEMs are moving to fan-out due to cost. Until the cost drops, many OEMs may stick to PoP, meaning the fan-out market for smartphones is limited. “The fan-out market may not be as substantial as it seems,” said Jérôme Azémar, an analyst with Yole, adding that the fan-out market could be headed towards a “bubble.”
Consequently, TSMC and the OSATs also are pushing fan-out in a number of markets beyond the smartphone. “We are talking about every possible combination,” ASE’s Wu said. “This could involve power management, baseband, automotive, consumer and industrial.”
In another trend, meanwhile, fan-out packages will involve both single- and multi-die solutions. “Heterogeneous integration will drive strong demand for fan-out WLP,” STATS ChipPAC’s Sikorski said. “New fan-out WLP business is by and large driven by laminate packages migrating to higher performance and lower cost fan-out designs. New OSAT TAM for fan-out WLP will be predominantly in the area of SiP designs. These designs will support increasingly complex functionality in electronic devices, particularly for mobile applications and emerging market segments, such as IoT, wearables, MEMS, sensor modules and infotainment.”
Meanwhile, another WLP market, fan-in, is also changing. In fan-in, the I/Os are placed over the solder balls. Fan-in packages are limited to about 200 I/Os and 0.6mm profiles.
Fan-in packages are low-cost solutions with small form factors, making them ideal for analog chips, power management ICs and RF devices. “Smartphone makers continue to use more and more fan-in WLPs and we expect this trend to continue,” TechSearch’s Vardaman said.
Fig. 2: Fan-in vs. fan-out wafer-level packaging. Source: STATS ChipPAC.
Fan-in is running into some competition against SiPs, however. SiPs are beginning to incorporate more power management and RF devices, which is taking a bite out of the fan-in market. This, in turn, has prompted Yole to lower its annual growth rate for fan-in packages from 9% to 6% from 2015 to 2021.
“A SiP is typically a single package with multiple components and multiple functions,” Amkor’s Huemoeller said. “As SiP proliferates in use for the mobile market, more of the packages typically tied to WLCSP are moving into the modules related to SiP. For example, integrated passive devices are ending up inside of SiP modules as individual components rather than standalone WLCSP.”
Fig. 3: Various packaging approaches. Source: STATS ChipPAC
Wirebond is still alive
2.5D and fan-out grab most of the headlines, but traditional wirebond packages still make up more than 80% of the overall chip packaging market. BGA, quad-flat packages and a plethora of legacy packages are based on wirebond. In total, the growth rate for wirebond packages is 6%, according to Kulicke & Soffa, a supplier of wire bonder equipment.
Developed in the 1950s, wire bonding is a fast and cheap solid-state welding process. Basically, a wire and a bond pad are bonded together using a wire bonder.
Fig. 4: Ultra fine pitch wire bonding. Source: Kulicke & Soffa.
The big shift occurred five or so years ago, when the industry moved from wirebonded packages using gold wires to copper wiring. Copper wiring lowered IC-packaging costs.
“Wirebond is still very strong,” ASE’s Wu said. “This year, we will buy more wire bonders for several reasons. First, we are trying to replace all of the older generation wire bonders. The devices are migrating to the higher end of the technology. Therefore, the wirebond pitch is becoming narrower. The newer generation wire bonders have better reliability and efficiency.”
There are other factors as well. “We continue to buy wire bonders because the market demands higher wirebond counts,” he said. “The third reason is that we continue to drive the copper wirebond for obvious cost reasons.”
Related Stories
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Making 2.5D, Fan-Outs Cheaper
Standards, new materials and different approaches are under development to drive 2.5D, 3D-ICs and fan-outs into the mainstream.
Packaging Wars Begin
OSATs and foundries begin to ramp offerings and investments in preparation for mainstream multi-chip architectures.
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