Learn about a FinFET process flow with various fin cut approaches to create a 3D model of a FinFET SRAM device.
In 5nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24nm. Fin depopulation is mandatory to enable area scaling, but it becomes challenging at small pitches. In the first part of our study, we simulate a FinFET process flow with various fin cut approaches to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part of our work, a process sensitivity analysis is performed to compare the impact of overlay and CD variations on various fin cut options.
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