tag: 2.5D

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

Stacking The Deck
By Javier DeLaCruz - 22 Aug, 2013 - Comments: 0

By Javier DeLaCruz The pinnacle of system-on-chip has passed. There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is that the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of through-silic... » read more

The New ASIC
By Javier DeLaCruz - 25 Jul, 2013 - Comments: 0

By Javier DeLaCruz The current state of the art For years, large ASICs like the ones used in network processing, supercomputing and high-end personal computing have had very interesting similarities. The figure below is a fairly typical floorplan of such an ASIC. After taping out over a dozen of these types of chips a year, it is interesting to see that the interfaces have changed, processo... » read more

MEMS Foundries Play Waiting Game
By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus For years, the foundries in the microelectromechanical systems (MEMS) business have been patiently waiting for the MEMS integrated device manufacturers (IDMs) to outsource some or all of their production. The MEMS foundries are still waiting for that development. Because MEMS are custom devices tuned to a proprietary process and toolset, IDMs still prefer to use their own f... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

The Rise Of Semiconductor IP Subsystems
By Various Writers - 11 Jul, 2013 - Comments: 0

The semiconductor IP (SIP) market arose when SIP vendors created IP functions that mirrored those found in the discrete semiconductor market and made those functions available to SoC designers in the form of hard or soft SIP blocks. As the SoC and SIP markets evolved, it was a natural evolution that many discrete SIP functions be converged into larger blocks that mimic system-level functions (i... » read more

Dealing With New Bottlenecks
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren�... » read more

New Approaches To Better Performance And Lower Power
By Ed Sperling - 11 Jul, 2013 - Comments: 0

By Ed Sperling Until 90nm, every feature shrink and rev of Moore’s Law included a side benefit of better power and performance. After that, improvements involved everything from different back-end processes to copper interconnects and transistor structures. But from 20nm onward, the future will rest with a combination of new materials, new architectures and new packaging approaches—and som... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest ... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest... » read more

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