tag: CDC

When Things Go Wrong Even When You’re Doing the Right Thing
By Joseph Hupcey III - 28 May, 2015 - Comments: 0

By Kurt Takara and Joe Hupcey III “Isolation. Retention. Level shifters. Dynamic voltage scaling. I’m doing all the right things to reduce the power consumption of my design by adding all of this power control logic. But because of this new low power circuitry, I’m seeing fresh clock domain crossing (CDC) problems that are making my design do all the wrong things; and my trusty old low... » read more

Clock Domain Crossing (CDC): Are We There Yet?
By Ravindra Aneja - 12 Mar, 2015 - Comments: 0

Over the last decade, SoC designs have become significantly reliant on IP reuse to manage the design complexity and meet time-to-market goals. IP-based design and verification methodology is essential but has put an additional verification burden on IP suppliers (internal and external). IP suppliers need to ensure that their IP is exhaustively verified and SoC Integrators need to ensure that al... » read more

User Case Study
By Joseph Hupcey III - 06 Nov, 2014 - Comments: 0

Whenever more than one clock is employed in an SoC (which is all SoCs), the risk of errors from clock domain crossings (CDC) – signals (or groups of signals) that are generated in one clock domain and consumed in another – is incredibly high. Unfortunately, CDC bugs are nearly impossible to catch with conventional simulations. Thus, all too often they escape into silicon. Debugging them in ... » read more

Where Do We Stand With CDC?
By Ann Mutschler - 26 Jun, 2014 - Comments: 1

Semiconductor Engineering sat down to discuss where the industry stands on clock domain crossing with Charlie Janac, CEO of Arteris; Shaker Sarwary, VP of Formal Verification Products at Atrenta; Pranav Ashar, CTO at Real Intent; and Namit Gupta, CAE, Verification Group at Synopsys. What follows are excerpts of that conversation. SE: While not a new aspect of design, clock domain crossing is... » read more

Rethinking Low Power Verification: LP + CDC Verification
By David Hsu - 12 Jun, 2014 - Comments: 1

In my last posting, we discussed some of the barriers that companies face in seeking to meet their low power verification objectives, and how the complete and integrated technologies in Synopsys’ new Verification Compiler product can help. This time, I’d like to introduce a relevant example of how unified technology solutions can help address complex design interactions in low power verific... » read more

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Blog Review: Jan. 22
By Ed Sperling - 22 Jan, 2014 - Comments: 0

Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder. Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe. Synopsys’ Richard Solomon has come up with a new definition for New Year’... » read more

SpyGlass Flow For Xilinx FPGA
By Various Writers - 04 Dec, 2013 - Comments: 0

As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?
By Ramesh Dewangan - 07 Nov, 2013 - Comments: 0

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

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