tag: lithography

Waiting For Next-Generation Lithography
By Mark LaPedus - 23 Jan, 2014 - Comments: 2

Nearly 30 years ago, optical lithography was supposed to hit the wall at the magical 1 micron barrier, prompting the need for a new patterning technology such as direct-write electron beam and X-ray lithography. At that time, however, the industry was able to push optical lithography for volume chip production at the 1-micron node and beyond. This, in turn, effectively killed direct-write e-... » read more

DSA, Multi-beam Make Steady Progress
By Mark LaPedus - 12 Dec, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss current and future lithography challenges with Laurent Pain, lithography lab manager at CEA-Leti. What follows are excerpts of that conversation. SE: CEA-Leti has two major programs in lithography. One is in directed self-assembly (DSA) and the other is in multi-beam e-beam. Let’s start with multi-beam. What is Leti doing in multi-beam and what... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Manufacturing Bits: Oct. 22
By Mark LaPedus - 22 Oct, 2013 - Comments: 0

Natural lithography For years, researchers have been exploring the development of nanosphere lithography or natural lithography. Nanosphere lithography makes use of directed self-assembly (DSA) techniques. The process begins with self-assembly of a nanosphere mask onto a substrate. This is followed by deposition of a material through the mask. The University of Paderborn has put a new twis... » read more

Reducing The Tapeout Crunch With Signoff Confidence
By Jean-Marie Brunet - 17 Oct, 2013 - Comments: 1

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays. At leading-edge nodes, however, we’re running into some new problems that need new solutions. We all know design rule numbers and complexity are going through the roof as we try to use 1... » read more

Multi-Beam Begins To Shine
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

After years of R&D and promises, multi-beam electron-beam technology is delayed and late to the market. The technology requires more funding and work than previously thought. And generally, the skepticism is running high for the technology. Finally, however, there is a ray of hope, and some momentum, in multi-beam—at least on the photomask front. Seeking to accelerate its multi-beam te... » read more

Debate Heats Up Over Bigger Glass
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

For more than two decades, photomask makers have been talking about moving to a new and larger mask size, sometimes called “bigger glass” by the industry. Generally, the discussions about “bigger glass” have been all talk and no action. But now, some chipmakers are turning up the volume in the discussions and are pushing for a larger mask size. A larger mask size would require the ph... » read more

Executive Briefing: Getting Direct On Litho
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down and talked with David Lam, principal of the David Lam Group, an investment and advisory firm. Lam is also the chairman of Multibeam, a multi-beam equipment startup for direct-write lithography and other applications. He founded Lam Research in 1980 and left as an employee in 1985. He served on Lam Research’s board for five years after that. SE: Multibeam ... » read more

Challenges Mount For EUV Masks
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

ASML Holding’s first production-worthy scanners for extreme ultraviolet (EUV) lithography are expected to ship this year, but there are still a number of challenges to bring the technology into high-volume manufacturing. As before, the three main challenges for EUV are the power sources, resists and photomasks. To date, the resists are making progress, while the EUV power sources remain a ... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

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