Week In Review: Auto, Security, Pervasive Computing


Automotive A fire at a Renesas fab may put a further squeeze on the supply of automotive chips, according to an Associated Press story. The fire in Naka Factory (located in Japan in Hitachinaka, Ibaraki Prefecture) was caused by plating equipment igniting within the first floor of the N3 Building and was extinguished the same day it started on March 19th, according to a press release. “The c... » read more

Week In Review: Design, Low Power


Companies Pearl Semiconductor launched to provide low and ultra-low noise timing products. “Pearl is a timing company developing resonator-agnostic solutions. We work with quartz crystals, MEMS resonators or whatever achieves superior performance,” said Ayman Ahmed, CEO of Pearl Semiconductor. “Current and future automotive applications demand low noise and a wide operating temperatur... » read more

Waiting For Chiplet Standards


The need and desire for chiplets is increasing, but for most companies that shift will happen slowly until proven standards are in place. Interoperability and compatibility depend on many layers and segments of the supply chain coming to agreement. Unfortunately, fragmented industry requirements may lead to a plethora of solutions. Standards always have enabled increasing specialization. ... » read more

Find Bugs Early: On-The-Fly Code Correction For Design And Verification Productivity


The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project stage multiplies the cost by ten. Bugs that escape verification and make their way to silicon are very expensive and time-consuming to fix. The ideal is to catch as many types of issues as possible as ... » read more

Demand for IC Resilience Drives Methodology Changes


Applications that demand safety, security, and resilience are driving new ways of thinking about design, verification, and the long-term reliability of chips on a mass scale. The need is growing for chips that can process more data faster, over longer periods of time, and often within a shrinking power budget. That, in turn, is forcing changes at multiple levels, at the architecture, design,... » read more

What Goes Wrong In Advanced Packages


Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

Blog Review: March 24


Arm's Brian Cline points to a project with GlobalFoundries to demonstrate the feasibility and readiness of high-density, face-to-face, wafer-bonded 3D stacking technologies for high performance, energy-efficient designs. Synopsys' Taylor Armerding warns that while supply chain security risks aren't new, the recent SolarWinds breach should make everyone pay much more attention to dependencies... » read more

Accelerate Custom Layout Using Custom Compiler’s User-Defined Device (UDD)


In this 7th video of the series, Kai Wang, Director of Engineering at Synopsys, discusses in-design electrical analysis, and why it is critical to use signoff engines to check and fix resistance, capacitance and electromigration issues during layout. Click here to access this video whitepaper. » read more

Week In Review: Design, Low Power


Qualcomm finalized its acquisition of data center chip startup Nuvia with a price of $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia’s technology wo... » read more

Blog Review: March 17


Synopsys' Chris Clark considers the growing number of automotive sensors and the cost/performance tradeoffs between edge computing capability, sensor fusion, sensor degradation, monitoring, and the maintenance of the software over the lifespan of a vehicle. Cadence's Paul McLellan checks out how the process of loading the bootstrap into memory has changed over the years, from hand-entered on... » read more

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