tag: Synopsys

Blog Review: March 4
By Jesse Allen - 04 Mar, 2020 - Comments: 0

Mentor's Shivani Joshi provides a primer on design rule checks and how they can help flag potential issues in PCB design. Synopsys' Taylor Armerding argues that while better IoT security requires a change in consumer culture and habits, manufacturers and government should be doing more as well. Cadence's Johnas Street chats with several colleagues about what Black History Month means to t... » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Feb, 2020 - Comments: 0

Tools Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys' automated debug system. Ansys released RaptorH, a tool that com... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 28 Feb, 2020 - Comments: 0

AI/Edge The United States Department of Defense (DOD) has adopted ethical principles for using artificial intelligence in warfare that chiefly say the U.S. has to follow the laws, treaties, in use of AI in warfare. Any AI used by DOD has to be responsible, equitable, traceable, reliable and governable. “The Department will design and engineer AI capabilities to fulfill their intended functio... » read more

Simulation: Go Parallel Or Go Home
By Taruna Reddy - 27 Feb, 2020 - Comments: 0

Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with the Universal Verification Methodology (UVM), and a large test suite. Constrained-random stimulus generation has largely replaced hand-crafted tests, but at the expense of much more simulation time. ... » read more

An Increasingly Complicated Relationship With Memory
By Brian Bailey - 27 Feb, 2020 - Comments: 4

The relationship between a processor and its memory used to be quite simple, but in modern SoCs there are multiple heterogeneous processors and accelerators, each needing a different means of accessing memory for maximum efficiency. Compromises are being made in order to preserve the unified programming model of the past, but the pressures are increasing for some fundamental changes. It does... » read more

The Cost Of Programmability
By Brian Bailey - 27 Feb, 2020 - Comments: 1

Nothing comes for free, and that is certainly true for the programmable elements in an SoC. But without them we are left with very specific devices that can only be used for one fixed application and cannot be updated. Few complex devices are created that do not have many layers of programmability, but the sizing of those capabilities is becoming more important than in the past. There are... » read more

LPDDR4/4X DRAM Variants and Possible System Configurations
By Synopsys - 26 Feb, 2020 - Comments: 0

LPDDR is the de-facto standard for main-memory targeting mobile applications such as smartphones and tablets. Low-Power Double Data Rate Synchronous Dynamic Random Access Memories (LPDDR SDRAMs) or DRAMS offer high-performance while consuming significantly lower power than standard DDR memories, such as DDR5/4/3, which are ideal for systems requiring large memory capacity. For this reason, LPDD... » read more

Hybrid Prototyping
By Ed Sperling - 26 Feb, 2020 - Comments: 1

David Svensson, applications engineer in Synopsys’ Verification Group, explains how a virtual transaction logic model can be connected to develop hardware-dependent drivers before RTL actually exists, why this is now critical for large, complex designs, and how to find the potential bottlenecks and debug both software and hardware. » read more

Blog Review: Feb. 26
By Jesse Allen - 26 Feb, 2020 - Comments: 0

Cadence's Paul McLellan listens in as Warren Savage of the University of Maryland explains how security threats are increasing as IoT devices broaden the attack surface and why the semiconductor industry needs to take responsibility. Synopsys' Taylor Armerding argues that a key first step to complying with new and upcoming consumer privacy laws should be ensuring cybersecurity to protect aga... » read more

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