Better Choreography Required For Complex Chips


The rapidly growing number of features and options in chip design are forcing engineering teams to ratchet up their planning around who does what, when it gets done, and how various components will interact. In effect, more elements in the design flow need to be choreographed much more precisely. Some steps have to shift further left, while others need to be considered earlier in the plannin... » read more

Blog Review: June 21


Synopsys' Vikram Bhatia identifies four trends driving the migration of EDA tools and chip design workloads to the cloud, from ever-increasing compute and time-to-market demands to advanced cybersecurity features. Cadence's Veena Parthan checks out how computational fluid dynamics and finite element analysis can help improve aquaculture with sustainable fish cage nets that minimize stagnatio... » read more

Week In Review: Design, Low Power


Intel released Tunnel Falls, its newest quantum research chip, to quantum computing researchers interested in using the 12-qubit silicon chip for their own experiments and research.  Intel is also providing the chips to research laboratories, with help from LQC (LPS Qubit Collaboratory) through the Army Research Office. The first labs to receive the chip are LPS, Sandia National Laboratories, ... » read more

CEO Outlook: Chiplets, Data Management, And Reliability


Semiconductor Engineering sat down to talk about changes in chip design with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; ... » read more

Blog Review: June 14


Synopsys' Richard Solomon and Gary Ruggles examine the Compute Express Link (CXL) protocol and how it could unlock new ways of doing computing such as enabling efficient heterogeneous computing architectures, accelerating data-intensive workloads, and facilitating advanced real-time analytics. Cadence's Andre Baguenie explains how to convert an electrical signal to a logic value using the Ve... » read more

EDA’s Role Grows For Preventing And Identifying Failures


The front end of design is becoming more tightly integrated with the back end of manufacturing, driven by the rising cost and impact of failures in advanced chips and critical applications. Ironically, the starting point for this shift is failure analysis (FA), which typically happens when a device fails to yield, or worse, when it is returned due to some problem. In production, that leads t... » read more

4 Ways To Design More Reliable Automotive Electronics


From engine management systems (fuel injection rate, emissions control, cooling systems) and autonomous controls (lane, speed, park assist, adaptive cruise control) to infotainment systems and comfort systems (climate control, electronic seat adjustment, automatic wipers, etc.), the modern-day gas-powered and electric vehicles have more electronic devices than ever. Indeed, the microprocessors ... » read more

Cold Plate Technology Comparison


New types of energy, such as wind and solar power, are being utilized more prevalently and hybrid cars/buses are being identified as a means of reducing carbon dioxide emissions resulting from the use of fossil fuels. Electronic systems like frequency converters for wind power and train utilization are required to provide ever higher levels of energy savings. As such, IGBT (insulated-gate bipol... » read more

Blog Review: June 7


Synopsys' Kenneth Larsen and Powerchip's S.Z. Chang explore wafer-on-wafer (WoW) and chip-on-wafer (CoW), 3D hybrid bonding schemes that can be used to stack memory on logic with shorter signal transmission distance at no wasted power and more interconnect and bandwidth density. In a podcast, Siemens' Conor Peick, Nand Kochhar, and Mark Sampson chat about how companies can address growing co... » read more

Blog Review: May 31


Cadence's Moshik Rubin looks at how the Portable Test and Stimulus Standard (PSS) is finding new use cases in ATE production test by enabling creation of a rich set of functional test scenarios in a reusable way. Synopsys' LJ Chen and Dana Neustadter check out the latest version of the Universal Flash Storage (UFS) standard, which doubles the data transfer rate of the preceding UFS 3.1 solut... » read more

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