When To Move To Multi-Die Assemblies


As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

Programmable Chips Evolve For Shifting Needs


ICs and SoCs are utilizing a range of processing elements that allow them to optimize current workloads while hedging their bets for the future. What used to be a simple choice between an ASIC, FPGA, or DSP, has evolved into a mix of processor types and architectures, including varying levels of programmability and customization. Speed is essential, but technology is evolving so quickly that... » read more

Chip Industry Week in Review


Government funding/defunding NIST is terminating funding for the SMART USA Institute, a CHIPS Act research center focused on digital twins, prompting congressional concern that the decision disrupts active awards and weakens U.S. semiconductor R&D commitments. Korea Zinc was awarded $210M in CHIPS Act funding towards a new $6.6B Tennessee advanced smelter and minerals processing facility,... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security


Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Blog Review: Dec. 17


Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Thermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies


As three-dimensional integrated circuit (3D-IC) technology becomes the architectural backbone of AI, high-performance computing (HPC), and advanced edge systems, thermal management has shifted from a downstream constraint to a fundamental design driver. The dense vertical integration that enables unprecedented performance also concentrates heat at levels that traditional two-dimensional design ... » read more

Limited by Power


AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

AI Buildout Makes HPC Simulation More Challenging


Simulations of semiconductors and systems are becoming bigger, more complex, and increasingly necessary, mirroring everything that is happening to the hardware itself — particularly in AI data centers. The move beyond monolithic chips to multi-die assemblies now requires solving some thorny multi-physics challenges, such as thermal and power delivery, which are increasingly difficult to mo... » read more

Chiplets Vs. Soft IP: Different In Almost Every Way


Chiplets serve a similar function as the soft IP widely used in chips today, but the similarities end there. While both can speed time to market and enable design teams to focus limited resources where they can best be applied, the implementation, manufacturing, test, and long-term business requirements wrought by a chiplet marketplace would be very different. Soft IP (also known as RTL IP) ... » read more

Arm Performance Cookbook: Your Guide to Optimal Design and Verification (EBook)


The Performance Cookbook for Arm is your essential resource for mastering the complexities of system-level performance, architecture exploration, and SoC verification. Why Download the Performance Cookbook? In-Depth Exploration - Dive into the evolution of Arm compute subsystem architectures, with detailed coverage on how critical components interact to deliver optimal performance be... » read more

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