tag: CDC

The Week In Review: Design
By Ed Sperling - 06 Jun, 2014 - Comments: 0

Tools Mentor Graphics rolled out embedded Linux software for AMD’s x86 G-series SoCs, code-named Steppe Eagle and its Crowned Eagle CPUs. Ansys-Apache and TowerJazz have created a power noise and reliability signoff design kit, including reference flow guidelines, test case examples and flow setup guidance. Synopsys updated its verification portfolio with static and formal tools for CD... » read more

Productive Clock Domain Crossing Verification
By Kiran Vittal - 08 May, 2014 - Comments: 2

Recently, we were invited to participate in an internal Chips@Cisco event along with other EDA vendors and FPGA providers. Executives from these vendors participated in a panel to discuss the challenges seen by the technology leaders in FPGAs and what it means to the industry. Everyone on the panel agreed that design size and complexity, including clock domains, is continuing to follow Moore’... » read more

Blog Review: Jan. 22
By Ed Sperling - 22 Jan, 2014 - Comments: 0

Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder. Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe. Synopsys’ Richard Solomon has come up with a new definition for New Year’... » read more

SpyGlass Flow For Xilinx FPGA
By Various Writers - 04 Dec, 2013 - Comments: 0

As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive alternative for system-on-chip (SoC) types of design. Large numbers of increasingly complex designs are now done with FPGAs, making verification a major task. Besides the usual issues of width mismatch, connectivity or synthesis-simulation mismatch, there are also problems related to multiple asynchronous clock domain... » read more

What Do Timing Constraints Have To Do With Clock Domain Crossing?
By Ramesh Dewangan - 07 Nov, 2013 - Comments: 0

As the complexity of designs has scaled, the need for complete and accurate timing constraints (defined typically as Synopsys Design Constraints or SDC) has become extremely critical. High quality timing constraints not only reduce the total effort required to achieve timing closure, but also reduce the number of iterations during that process. In the worst case, incorrect timing constraints ca... » read more

CDC Verification Of Billion-Gate SoCs
By Various Writers - 07 Nov, 2013 - Comments: 0

Driven by growing design sizes and complexities and aggressive power requirements, design and verification engineers are witnessing an explosion in the number of asynchronous clocks. Consequently, design and verification teams spend a huge amount of time verifying the correctness of asynchronous boundaries on the chip. The paper describes three methodologies to address this issue and the benefi... » read more

CDC Methodology For Fast-To-Slow Clocks
By Various Writers - 24 Oct, 2013 - Comments: 0

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC identifies all the data and associated control paths in a design and will ensure that the control signals passing fr... » read more

Avoiding Pitfalls While Specifying Timing Exceptions
By Various Writers - 08 Aug, 2013 - Comments: 0

Timing exceptions are commonly used to meet timing goals while implementing a design. These exceptions typically cover asynchronous paths like clock domain crossings (CDC) or synchronous paths where timing is either not relevant (e.g., set_false_path command in SDC) or can be relaxed (e.g., set_multicycle_path command in SDC), instructing static timing analysis (STA) and implementation tools to... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

Clock Domain Crossing Demystified
By Various Writers - 25 Apr, 2013 - Comments: 0

A look at the second-generation solution for CDC verification. To download this white paper, click here. » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy