All AI Data Center Interconnects Will Be Optical Within 5 Years


I spent several days at OFC (Optical Fiber Communications Conference) 2026 in LA. The crowds were huge and the enthusiasm intense. Long-time attendees noted the shift from telecom to data center AI in just a few years. Nvidia GTC 2026 took place simultaneously in San Jose. OFC and GTC are entangled because data center AI needs optical interconnect to keep compute fed. Optical interconnect... » read more

Why Co-Packaged Optics Should be Viewed as an Architectural Commitment (UW-Madison, MIT et al.)


A new technical paper, "3D optoelectronics and co-packaged optics: when solving the wrong problems stalls deployment," by the University of Wisconsin, MIT, and Invictus Innovation EV Technology. Abstract "The rapid growth of AI and accelerator-driven workloads is forcing a fundamental rethinking of optical interconnect architectures in datacenters. Co-packaged optics and three-dimensional... » read more

Scaling AI Infrastructure: Overcoming Interconnect Bottlenecks Via CPO And Heterogeneous Integration


The rapid evolution of Artificial Intelligence (AI) has surpassed the capabilities of traditional monolithic compute architectures. The industry is shifting toward a systemic approach, where large-scale distributed clusters of GPUs/AI accelerators function as a single, unified computational engine to support the next generation of trillion-parameter models. Co-packaged optics (CPO) offers s... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers


Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

Verifying Scale-Up And Scale-Out In Data Centers


Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

Laser Arrays May Simplify Co-Packaged Optics


Key Takeaways Moving photonic ICs into the same package as silicon helps improve performance, but lasers remain outside. A new monolithic laser array allows hundreds of colors, each individually software-tunable New options are being turned into products, which could help commercialize CPO. The move to co-packaged optics (CPO) holds the promise of putting photonic ICs (PICs)... » read more

Silicon Photonics In The Data Center: What A CMOS Exec Needs To Know


Silicon Photonics is changing the data center, with the biggest changes still ahead. Figure 1: Google Jupiter Network for multi-thousand Ironwood TPU clusters. Source: Google Refresher for new readers: Data centers contain hundreds or thousands of racks. For example, the Nvidia GB200 NVL72 AI compute/switch rack is about 24 inches wide, about 88 inches high and 42 inches deep. I... » read more

Overview and Comparison of Devices Used For Optical Waveguide-to-Waveguide Coupling (MIT et al.)


A new technical paper titled "Advances in waveguide to waveguide couplers for 3D integrated photonic packaging" was published by researchers at MIT and Bridgewater State University. Abstract "In this paper, we provide an overview and comparison of devices used for optical waveguide-to-waveguide coupling including inter-chip edge couplers, grating couplers, free form couplers, evanescent cou... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities


Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Advanced Packaging: A Key Technology For The Next Generation Of Electronics


In recent years, advanced packaging has become much more important. While semiconductor manufacturers used to focus primarily on miniaturization and increasing the performance of individual chips, the focus is increasingly shifting to the system level: How can processor cores, memory, sensors, and wireless modules be integrated as efficiently, compactly, and powerfully as possible within a sing... » read more

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