tag: CPO

Scaling AI Infrastructure: Overcoming Interconnect Bottlenecks Via CPO And Heterogeneous Integration
By Vincent Lin - 19 Mar, 2026 - Comments: 0

The rapid evolution of Artificial Intelligence (AI) has surpassed the capabilities of traditional monolithic compute architectures. The industry is shifting toward a systemic approach, where large-scale distributed clusters of GPUs/AI accelerators function as a single, unified computational engine to support the next generation of trillion-parameter models. Co-packaged optics (CPO) offers s... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0

Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities
By Cassandra Melvin - 18 Dec, 2025 - Comments: 0

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Can Today’s Processor Architectures Be More Efficient?
By Bryon Moyer - 17 Jul, 2025 - Comments: 3

For years, processors focused on performance, and that performance had little accountability to anything else. Performance still matters, but now it must be accountable to power. If small gains in performance result in disproportionate power gains, designers may need to discard such improvements in favor of more power-efficient ones. Although current architectures undergo a steady cadence of... » read more

Integration of High-Density Polymer Waveguides With Silicon Photonics for CPO (imec, Ghent)
By Technical Paper Link - 03 Jun, 2025 - Comments: 0

A technical paper titled "Low-Loss Integration of High-Density Polymer Waveguides with Silicon Photonics for Co-Packaged Optics" was published by researchers at imec and Ghent University. Abstract "Co-Packaged Optics applications require scalable and high-yield optical interfacing solutions to silicon photonic chiplets, offering low-loss, broadband, and polarization-independent optical coup... » read more

Co-Packaged Optics Reaches Power Efficiency Tipping Point
By Laura Peters - 02 Jun, 2025 - Comments: 0

Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Co-Packaged Optics To Train/Run GenAI Models in Data Centers (IBM)
By Technical Paper Link - 27 Dec, 2024 - Comments: 0

A new technical paper titled "Next generation Co-Packaged Optics Technology to Train & Run Generative AI Models in Data Centers and Other Computing Applications" was published by researchers at IBM. Abstract "We report on the successful design and fabrication of optical modules using a 50 micron pitch polymer waveguide interface, integrated for low loss, high density optical data transf... » read more

Linear Drive Optics May Reduce Data Latency
By Karen Heyman - 11 Apr, 2024 - Comments: 0

Optical and electrical are starting to cross paths at a much deeper level, particularly with the growing focus on 3D-ICs and AI/ML training in data centers, driving changes both in how chips are designed and how these very different technologies are integrated together. At the root of this shift are the power and performance demands of AI/ML. It can now take several buildings of a data cente... » read more

Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers
By Synopsys - 27 Oct, 2021 - Comments: 0

Driven by a need to reduce power and increase bandwidth density in data center network switches and other devices, the data networking industry is moving toward adoption of co-packaged optics (CPO). This paper provides a brief overview of the history of copper and optical interconnects, the limitations of existing interconnect solutions, and the future of co-packaged optics, including the benef... » read more

Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes
By Suresh Andani - 14 May, 2020 - Comments: 0

Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

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