tag: Dassault Systemes

Blog Review: July 10
By Ed Sperling - 10 Jul, 2013 - Comments: 0

By Ed Sperling Mentor’s Harry Foster rolls out part four of his epic functional verification study, this one on design and verification reuse. If you work in the verification world, pounce. Cadence’s Brian Fuller looks back over a quarter century of technology—and what the average salary of a hardware design engineer will be in a 15 years: $499,000. But what will a cup of coffee cost?... » read more

The Week In Review: July 8
By Ed Sperling - 08 Jul, 2013 - Comments: 0

By Ed Sperling Mentor Graphics put into place a second shareholder rights to plan to ward off hostile takeovers. This one increases the threshold for triggering the rights plan to 20% of common stock from the previous 15%, and allows a qualifying offer provision that allows the board to call a special meeting provided the exercise price per right is increased to $90 from $65. It also extends ... » read more

De-Mystifying The SoC Supply Chain
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Barbara Jorgensen At the heart of every supply chain operation is the desire to mitigate risk. In theory, a supply chain allows a customer to leverage the best of the best in technology, logistics or production at a lower cost than DIY (do it yourself.) The system on chip (SoC) supply chain is no different—there’s a whole ecosystem in the semiconductor industry that supports design, pro... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

The Week In Review: May 31
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Mentor Graphics and GlobalFoundries teamed up to deliver 20nm design kits that include Mentor’s place and route tool, including verification and conflict resolution engines for double-patterning violations. The 20nm process is used for GlobalFoundries’ 14nm finFETs. Mentor also received 16nm finFET certification from TSMC for the same tools plus its physical verification pl... » read more

Experience Required
By The SE Staff - 30 May, 2013 - Comments: 0

Many prominent semiconductor, EDA and IP companies are acknowledging the influence of user-experience design methodologies and technologies on their business. Experiences are the evolution of commoditization (chip hardware) and customization (software). But many design engineers remain cautious about the actual application of experiences to their work. What is driving this emphasis on expe... » read more

Beyond Software: The Virtual-Machine Supply System
By The SE Staff - 25 Apr, 2013 - Comments: 0

It’s no secret that EDA and IP companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Around 2000, the industry was very fragmented. Mobile-chip and IP vendors worked with handset makers, who then partnered with operating-system (OS) suppliers and finally network operators. The next 12 years resulted in various combinati... » read more

More Than Data Management
By Ann Mutschler - 28 Mar, 2013 - Comments: 0

By Ann Steffora Mutschler Managing the people, the data and the technology are just as important as meeting the market window given that without these, the entire project wouldn’t function. Throw huge data set sizes, different cultures and business management issues into the mix and the challenges are many. Fortunately, these are issues that the semiconductor industry has been refining for ... » read more

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