The Data Center Journey, From Central Utility To Center Of The Universe


High-performance computing (HPC) has taken on many meanings over the years. The primary goal of HPC is to provide the needed computational power to run a data center – a utilitarian facility dedicated to storing, processing, and distributing data. The beginning of HPC Historically, the data being processed was the output of business operations for a given organization. Transactions, custome... » read more

A New Era For HPC-Driven Engineering Simulation


Market pressure and technological advancements have rapidly changed the way engineers work. Design engineers increasingly work with larger and more complex models, must conduct more frequent simulation analysis, and iterate more rapidly. Compute constraints, however, often result in engineers limiting model sizes and simulation fidelity, or relying on lengthy, overnight simulation runs. ... » read more

The Value Of High-Performance Computing For Simulation


This white paper breaks down the costs and time savings associated with implementing high-performance computing technology. High-performance computing (HPC) is an enormous part of the present and future of engineering simulation. HPC allows best-in-class companies to gain high-fidelity insight into product behavior, insight that cannot be obtained without the detailed simulation models – i... » read more

How New Storage Technologies Enhance HPC Systems


High-performance computing (HPC) has historically been available primarily to governments, research institutions, and a few very large corporations for modeling, simulation, and forecasting applications. As HPC platforms are being deployed in the cloud for shared services, high-performance computing is becoming much more accessible, and its use is benefiting organizations of all sizes. Increasi... » read more

Center Stage: The Time For Hybrid Bonding Has Arrived


When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung, or Huawei in your hands. ... » read more

Choosing The Right Server Interface Architectures For High Performance Computing


The largest bulk and cost of a modern high-performance computing (HPC) installation involves the acquisition or provisioning of many identical systems, interconnected by one or more networks, typically Ethernet and/or InfiniBand. Most HPC experts know that there are many choices between different server manufacturers and the options of form factor, CPU, RAM configuration, out of band management... » read more

Analytical Energy Model Parametrized by Workload, Clock Frequency and Number of Active Cores for Share-Memory High-Performance Computing Applications


New academic paper from University of Mons (Belgium) and Universidade Federal do Rio Grande do Norte (Brazil). Abstract "Energy consumption is crucial in high-performance computing (HPC), especially to enable the next exascale generation. Hence, modern systems implement various hardware and software features for power management. Nonetheless, due to numerous different implementations, we ca... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems


Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Domain-Specific Design Drives EDA Changes


The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

A Broad Look Inside Advanced Packaging


Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion. SE: Where are we in the semiconductor cycle right now? Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. ... » read more

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