tag: Lam Research

Chip Shortages Grow For Mature Nodes
By Mark LaPedus - 22 Jul, 2021 - Comments: 0

The current wave of chip shortages is expected to last for the foreseeable future, particularly for a growing list of critical devices produced in mature process nodes. Chips manufactured at mature nodes typically fall under the radar, but they are used in nearly every electronic device, including appliances, cars, computers, displays, industrial equipment, smartphones, and TVs. Many of thes... » read more

MicroLEDs Moving From Lab to Fab
By Laura Peters - 22 Jul, 2021 - Comments: 1

Every disruptive technology has its "aha" moment — the time when everyone from engineers to investors realizes that, yes, this technology is the real deal and it won’t be scrapped on the R&D floor. For many, it was Samsung’s recent announcement of a 110-inch microLED TV that irrevocably put microLEDs on the map. The TV’s price is $155,000, but as with most consumer electronics th... » read more

Using Less Helium In Semiconductor Manufacturing
By Terry Powell - 22 Jul, 2021 - Comments: 0

Helium gas is increasingly in short supply. While consumers may be most familiar with it for use in filling balloons, it is used much more heavily in a variety of industrial processes – including semiconductor fabrication. As a result of supply concerns, many companies, including Lam, are looking for ways to reduce their helium usage. The making of a semiconductor chip involv... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Blog Review: July 21
By Jesse Allen - 21 Jul, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Partha Ranganathan of Google argues that a new era of Moore's Law is emerging, defined both by the efficient design of hardware accelerators and improving the ways that hardware is utilized. Siemens EDA's Chris Spear continues exploring classes in SystemVerilog with a look at the relationship between the class variables that point to an object and how to... » read more

The Effects Of Poly Corner Etch Residue On Advanced FinFET Device Performance
By Coventor - 21 Jul, 2021 - Comments: 0

In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy an... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 02 Jul, 2021 - Comments: 0

Chipmakers and OEMs More delays and product woes at Intel. “INTC disclosed that it is delaying the launch of its next-generation Xeon server processor Sapphire Rapids (10nm) from the end of this year to 1Q22 due to additional validation needed for the chip,” said John Vinh, an analyst at KeyBanc, in a research note. “Production is expected to begin in 1Q22, with the ramp expected to begi... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 02 Jul, 2021 - Comments: 0

Security The U.S. government agencies put out a warning that Russian military has been using a Kubernetes cluster to attempt distributed and anonymized brute force access against hundreds of government and private sector targets worldwide. Department of Homeland Security (DHS)’s Cybersecurity and Infrastructure Security Agency (CISA), the Federal Bureau of Investigation (FBI), the National S... » read more

Blog Review: June 30
By Jesse Allen - 30 Jun, 2021 - Comments: 0

Siemens EDA's Chris Spear considers what classes should represent in SystemVerilog and offers two major categories along with some helpful UVM tips. Cadence's Paul McLellan listens in on keynotes at the recent TSMC Technology Symposium, including TSMC CEO C. C. Wei's introduction some of the fab's new offerings, such as an automotive-focused N5 process. Synopsys' Dennis Kengo Oka notes th... » read more

Blog Review: June 23
By Jesse Allen - 23 Jun, 2021 - Comments: 0

Synopsys' Manuel Mota shows how splitting SoCs into smaller dies for advanced packaging and using die-to-die interfaces to enable high bandwidth, low latency, and low power connectivity can benefit hyperscale data centers. Siemens EDA's Chris Spear explains the relationship between classes and objects in SystemVerilog with a handy visualization and notes the difference between SystemVerilog ... » read more

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