Bumps Vs. Hybrid Bonding For Advanced Packaging


Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Fan-Out Packaging Options Grow


Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

Finding, Predicting EUV Stochastic Defects


Several vendors are rolling out next-generation inspection systems and software that locates problematic defects in chips caused by processes in extreme ultraviolet (EUV) lithography. Each defect detection technology involves various tradeoffs. But it’s imperative to use one or more of them in the fab. Ultimately, these so-called stochastic-induced defects caused by EUV can impact the perf... » read more

Using Virtual Process Libraries To Improve Semiconductor Manufacturing


People think that semiconductor process simulation libraries should be developed using a perfect theoretical background that is strongly supported by empirical data. This might be true in academic research, where researchers are trying to develop a systematic approach to understanding a process mechanism. However, it is definitely not true in production fabs, where engineers need to quickly a... » read more

Process Model Calibration: The Key To Building Predictive And Accurate 3D Process Models


The semiconductor industry has always faced challenges caused by device scaling, architecture evolution, and process complexity and integration. These challenges are coupled with a need to provide new technology to the market quickly. In the initial stages of semiconductor technology development, innovative process flow schemes must be tested using silicon test wafers. These wafer tests are len... » read more

Week In Review: Manufacturing, Test


Chipmakers SiFive has received a takeover offer from Intel, according to a report from Bloomberg. The asking price is more than $2 billion. ------------------------------------------------------------------ IBM has filed suit against GlobalFoundries (GF), alleging fraud and breach of contract committed by GF. IBM’s suit, filed in the Supreme Court of the state of New York, seeks relief... » read more

Blog Review: Jun 9


Arm's Partha Maji introduces a collaboration with the University of Cambridge to advance Bayesian statistics and probabilistic machine learning, which could play a vital role in safety-critical AI applications. Siemens' Thomas Dewey looks at a way to improve autonomous driving capabilities by enabling vehicles to train on past hazardous situations to provide and early warning for when they m... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing — IoT, edge, cloud, data center, and back To simplify IoT workflows, Arm announced that it is putting parts of its Common Microcontroller Software Interface Standard (CMSIS) into an open project called Open-CMSIS-Pack. The CMSIS is a vendor-independent abstraction layer for MCUs, especially Arm Cortex-M processors, that makes it possible for developers to deal with softwa... » read more

Principles, Applications, And The Future Of Piezoelectric MEMS


Piezoelectricity is a property of certain materials to become electrically polarized under strain and stress. This phenomenon has been studied extensively since it was first discovered in the mid-18th century. Piezoelectric materials can generate an electric charge in response to an applied mechanical stress and can also generate mechanical stress upon an applied electrical charge. These mater... » read more

The Increasingly Uneven Race To 3nm/2nm


Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

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