Blog Review: Nov. 23


Mentor's Brian Derrick argues that both designers and ecosystems are changing to leverage advances in sensing technology at the edge of the IoT. Cadence's Paul McLellan listens in on a DVCon Europe keynote by NXP's Jürgen Weyer on what automotive is learning from mobile and where the big challenges lie. Synopsys' Tumuluri SantoshaLakshmi talks about seven of the biggest challenges in JED... » read more

Avoiding The Barriers For Multi-Board Systems Design Development


Designing electronic systems that comprise multiple interacting boards, connectors and cables requires a multi-discipline team collaboration to effectively manage design complexity for optimum product performance and reliability. Multi-board systems may comprise two boards or up to hundreds of boards, packing a cabinet or rack, with interconnected connectors and/or cables. Since the hardware fu... » read more

Homogeneous And Heterogeneous Computing Collide


Eleven years ago processors stopped scaling due to diminishing returns and the breakdown of [getkc id="213" kc_name="Dennard's Law"]. That set in motion a chain of events from which the industry has still not fully recovered. The transition to homogeneous multi-core processing presented the software side with a problem that they did not know how to solve, namely how to optimize the usage of ... » read more

The Limits Of Parallelism


Parallelism used to be the domain of supercomputers working on weather simulations or plutonium decay. It is now part of the architecture of most SoCs. But just how efficient, effective and widespread has parallelism really become? There is no simple answer to that question. Even for a dual-core implementation of a processor on a chip, results can vary greatly by software application, operat... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

New Wave Of Consolidation


Consolidation is picking up again across the semiconductor industry, against a backdrop of looming interest rate hikes, geopolitical uncertainty, and the erosion of longstanding demarcations between markets. In the past couple of weeks, Siemens signed a deal to buy [getentity id="22017" e_name="Mentor Graphics"] for $4 billion, and [getentity id="22865" e_name="Samsung"] purchased Harman, a ... » read more

The Week In Review: Design


M&A Siemens plans to buy Mentor Graphics for $4.5 billion in cash. The move, if approved by regulators, would greatly expand Siemens’ capabilities in multi-physics design and embedded software for everything from semiconductors to automotive wiring harnesses. The transaction is expected to close in the second quarter of 2017. Tools Mentor Graphics uncorked a new product to measur... » read more

More EUV Mask Gaps


Extreme ultraviolet (EUV) lithography is at a critical juncture. After several delays and glitches, [gettech id="31045" comment="EUV"] is now targeted for 7nm and/or 5nm. But there are still a number of technologies that must come together before EUV is inserted into mass production. And if the pieces don’t fall into place, EUV could slip again. First, the EUV source must generate more ... » read more

Fill/Cut Self-Aligned Double-Patterning


By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke Self-aligned double patterning (SADP) is an alternative double-patterning process to the traditional litho-etch-litho-etch (LELE) approach used in most advanced production nodes. The main difference between the two approaches is that in LELE, the layout is divided between two masks, and the second mask is aligned with resp... » read more

Mastering The Magic Of Multi-Patterning


Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on y... » read more

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