Special Report: Using FPGAs For 3D Stacking


By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Corners Up, Margins Down


By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

The Road To DAC: One On One With Wally Rhines


Mentor Graphics' CEO talks with Low-Power Engineering about the cost of designing a chip, the rising percentage of embedded software, the shift to FPGAs and what's changing in EDA. [youtube vid=Zjs9xz4iD3E] » read more

The Great Divide


By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation


By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

Unified Design Flows Require New Skill Sets


By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more

How Good Is Good Enough?


By Jon McDonald I’ve heard a few comments recently questioning how good is good enough. How good does a device have to be before it’s above questioning its capabilities? When designing some new whiz-bang device how do we know when we can stop? I think most engineers will agree there is always room for improvement. There are additional optimizations, refinements or alternative approaches... » read more

Same Industry, Different Shape


As the design industry plunges into DAC this year, it’s beginning to look like a completely different industry. It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of... » read more

It’s The Architecture


Power optimization is a system issue. How many times have you experienced your cell phone provider sending your phone an update and the battery lifetime then improving? The hardware team built in the hooks but there just wasn't enough time to get the software together and tested before the product needed to ship, so the improved functionality shipped later. Well, that's at least one advanta... » read more

A Shock To The System


By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

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