tag: Siemens EDA

Meeting The Challenge Of Verification In Low-Power Designs
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Cheryl Ajluni Over the years, new techniques, technologies and design tools have been brought to market with the explicit intent of simplifying design verification. Despite these efforts verification still manages to consume a huge chunk of the time spent during design. By some accounts that number tops 70%. The problem is that verification is hard, and it certainly doesn’t get an easi... » read more

Hypervisors For Managing Power
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Ed Sperling Hypervisors are headed for a new role inside of multicore chips—managing the various power islands in addition to the cores. A patent application filed by IBM, entitled “Method and syarstem for hypervisor based power management,” shows the company’s intention to use hypervisors for everything from monitoring power consumption rates to scaling power for individual core... » read more

Power Trip Advisor
By Ed Sperling - 12 Nov, 2009 - Comments: 0

By Geoffrey James There’s never been a greater demand for power-efficient silicon. As consumer electronic devices get smaller, with increased functionality, battery power becomes a premium resource. At the same time, “Green IT” is a major corporate trend, and the best way to be environmentally sensitive (while saving on energy costs) is to buy technology that ekes the maximum computing o... » read more

The FPGA Alternative
By Various Writers - 31 Oct, 2009 - Comments: 0

By Geoffrey James Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to be useful for much more than prototyping. Today, however, designers are increasingly turning to FPGAs for their SOC targets for production systems. Why the sudden upsurge in So... » read more

The Abstraction of Test
By Ann Mutschler - 29 Oct, 2009 - Comments: 0

By Ann Steffora Mutschler By now, semiconductor design abstraction is old hat to many engineers, but mention the term “semiconductor test abstraction” and expect a blank stare in return. Design complexity, enormous design size, and short market windows have put tremendous pressure on test to occur earlier rather than later. Even at the RTL level, where hardware test typically has not ... » read more

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

A High-Level Model For Reducing Frustration
By Jon McDonald - 24 Sep, 2009 - Comments: 0

By Jon McDonald Earlier this week I was sitting in the airport waiting for my flight 
to depart. I was connecting through Atlanta. This happened to be one of the days that Atlanta was receiving heavy rains causing flooding 
and occasionally closing the airport. First the flight to Atlanta was 
delayed an hour, then two, then three. Meanwhile my connecting flight 
had been c... » read more

Verification As A Deterrent?
By Ed Sperling - 24 Sep, 2009 - Comments: 0

By Ed Sperling Verification is becoming more than a bottleneck in semiconductor design. It’s actually deterring companies from adopting the latest techniques for saving power or building certain features into chips. The problem is one of complexity, and it’s getting worse at every node. While the tools exist to do complex designs, there are the classic tradeoffs of area, power and per... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 04 Sep, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power a... » read more

Experts At The Table: Building A Better Mousetrap
By Ed Sperling - 28 Aug, 2009 - Comments: 0

Low-Power Design sat down with Richard Zarr, chief technologist for the PowerWise Brand at National Semiconductor; Jon McDonald, technical marketing engineer in Mentor Graphics’ design creation business unit; Prasad Subramaniam, vice president of design technology at eSilicon; Steve Carlson, vice president of marketing at Cadence Design Systems, and David Allen, product director for power at ... » read more

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