Chip Industry Week In Review

By The SE Staff - 13 Mar, 2026 - Comments: 0

Disruptions caused by the Iran conflict have taken about one third of the global helium supply off the market, an essential gas for semiconductor manufacturing, reports the World Economic Forum. Other potential impacts for the chip industry include bromine and other chemical shortages, logistical disruptions, and higher energy prices incurred by fabs in Asia. Top Deals IBM and Lam R... » read more

Chip Industry Technical Paper Roundup: Mar. 9

By Linda Christensen - 09 Mar, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations FHECore: Rethinking GPU Microarchitecture for Fully Homomorphic Encryption 🔗 Boston University, Northeastern University, KAIST, University of Murcia Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler ... » read more

10-Year Roadmap for AI + Hardware (UIUC, UCLA, Stanford et al.)

By Technical Paper Link - 06 Mar, 2026 - Comments: 0

Researchers from University of Illinois Urbana-Champaign, UCLA, Stanford University, Nvidia, Google, et al. have released “AI+HW 2035: Shaping the Next Decade”. Abstract “Artificial intelligence (AI) and hardware (HW) are advancing at unprecedented rates, yet their trajectories have become inseparably intertwined. The global research community lacks a cohesive, long-term vision t... » read more

Optimal Heterogeneous Memory Configs for AI Tasks Under Specified Performance Metrics (Stanford, UCSC)

By Technical Paper Link - 01 Mar, 2026 - Comments: 0

Researchers from Stanford University and University of California, Santa Cruz have released “Heterogeneous Memory Design Exploration for AI Accelerators with a Gain Cell Memory Compiler”. Abstract “As memory increasingly dominates system cost and energy, heterogeneous on-chip memory systems that combine technologies with complementary characteristics are becoming essential. Gain ... » read more

Chip Industry Week in Review

By The SE Staff - 20 Feb, 2026 - Comments: 0

The IEEE ISSCC conference was held this week in San Francisco. Among the highlights: IBM detailed an AI accelerator based on its new inferencing dataflow architecture. CEA-Leti presented a chip-scale, ultra-fast, battery-operated EPR spectrometer. QuTech introduced a cryo-CMOS SoC with NV centers in diamond. UTokyo showed its low-jitter PLL architecture for beyond 5G/6G. Imec d... » read more

Research Bits: Feb. 17

By Jesse Allen - 17 Feb, 2026 - Comments: 0

Analog layout foundation model Researchers from Pohang University of Science and Technology (POSTECH) built a foundation model for automated analog circuit layout. The team used a self-supervised learning approach, in which the model learns without human-provided labels. To counter a lack of available training data, the team divided analog layouts into small patches, masked part of each lay... » read more

Chip Industry Week In Review

By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections. Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

Oxides Bring Low Leakage Transistors To Leading-Edge Memories

By Katherine Derbyshire - 22 Jan, 2026 - Comments: 1

AI workloads need to position more memory that uses less power in ever-closer proximity to computational logic. That overriding imperative is driving new memory designs and new materials exploration across a wide range of applications, including cache memory, working memory, as well as a new category, non-volatile memory used for direct computation. The largest of these, by volume, is workin... » read more

Research Bits: Jan. 12

By Jesse Allen - 12 Jan, 2026 - Comments: 0

Wafer-scale two-photon lithography Researchers from Lawrence Livermore National Laboratory (LLNL) and Stanford University demonstrated a two-photon lithography (TPL) platform for wafer-scale manufacturing. The TPL platform uses large arrays of metalenses to split a femtosecond laser into more than 120,000 coordinated focal spots that write simultaneously across centimeter-scale areas. The a... » read more

Chip Industry Week in Review

By The SE Staff - 09 Jan, 2026 - Comments: 0

SIA's latest monthly global semiconductor sales report reflects a ~30% YOY increase, hitting a record $75.3B in November 2025. Asia Pacific had a notable 66% increase. Cadence launched its Chiplet Spec-to-Packaged Parts ecosystem to accelerate time to market for chiplet development for physical AI, data centers, and HPC applications. Initial IP partners joining Cadence include Arm, Arteris, ... » read more

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tag: Stanford University

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: Mar. 9

10-Year Roadmap for AI + Hardware (UIUC, UCLA, Stanford et al.)

Optimal Heterogeneous Memory Configs for AI Tasks Under Specified Performance Metrics (Stanford, UCSC)

Chip Industry Week in Review

Research Bits: Feb. 17

Chip Industry Week In Review

Oxides Bring Low Leakage Transistors To Leading-Edge Memories

Research Bits: Jan. 12

Chip Industry Week in Review

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